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Searched refs:eventq_irq_cfg0 (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu/qemu-6.2.0/include/hw/arm/
H A Dsmmuv3.h57 uint64_t eventq_irq_cfg0;
/dports/emulators/qemu60/qemu-6.0.0/include/hw/arm/
H A Dsmmuv3.h57 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu5/qemu-5.2.0/include/hw/arm/
H A Dsmmuv3.h57 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/arm/
H A Dsmmuv3.h57 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/
H A Dsmmuv3.h55 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/
H A Dsmmuv3.h55 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/arm/
H A Dsmmuv3.h55 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/arm/
H A Dsmmuv3.h55 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/arm/
H A Dsmmuv3.h55 uint64_t eventq_irq_cfg0; member
/dports/emulators/qemu42/qemu-4.2.1/hw/arm/
H A Dsmmuv3.c1083 s->eventq_irq_cfg0 = data; in smmu_writell()
1179 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1182 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1459 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/
H A Dsmmuv3.c1083 s->eventq_irq_cfg0 = data; in smmu_writell()
1179 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1182 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1459 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/
H A Dsmmuv3.c1065 s->eventq_irq_cfg0 = data; in smmu_writell()
1161 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1164 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1441 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu5/qemu-5.2.0/hw/arm/
H A Dsmmuv3.c1081 s->eventq_irq_cfg0 = data; in smmu_writell()
1177 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1180 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1461 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/
H A Dsmmuv3.c1081 s->eventq_irq_cfg0 = data; in smmu_writell()
1177 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1180 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1457 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/
H A Dsmmuv3.c1081 s->eventq_irq_cfg0 = data; in smmu_writell()
1177 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1180 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1457 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu/qemu-6.2.0/hw/arm/
H A Dsmmuv3.c1113 s->eventq_irq_cfg0 = data;
1209 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data);
1212 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data);
1493 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu60/qemu-6.0.0/hw/arm/
H A Dsmmuv3.c1110 s->eventq_irq_cfg0 = data; in smmu_writell()
1206 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1209 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1490 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/
H A Dsmmuv3.c1113 s->eventq_irq_cfg0 = data; in smmu_writell()
1209 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); in smmu_writel()
1212 s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); in smmu_writel()
1493 VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),