| /dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
|
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
|
| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
|
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
|
| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
|
| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
|
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
|
| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
|
| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
|
| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
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| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
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| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
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| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
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| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
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| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
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| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vuzp.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
31 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
41 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
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| H A D | vtrn.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
19 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, variable
23 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
30 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
37 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
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| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
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| /dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vzip.c | 7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, variable
26 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
32 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
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