/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 178 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 182 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 186 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 537 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 538 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 539 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 540 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 541 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 543 CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 546 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 178 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 182 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 186 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 537 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 538 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 539 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 540 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 541 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 543 CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 546 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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H A D | bf16_vstN_lane_1.c | 46 VECT_VAR_DECL(expected_st4_2,hbfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable 47 VECT_VAR_DECL(expected_st4_2,hbfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable 211 CHECK_FP(TEST_MSG, bfloat, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 212 CHECK_FP(TEST_MSG, bfloat, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane()
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/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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H A D | bf16_vstN_lane_1.c | 46 VECT_VAR_DECL(expected_st4_2,hbfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable 47 VECT_VAR_DECL(expected_st4_2,hbfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable 211 CHECK_FP(TEST_MSG, bfloat, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 212 CHECK_FP(TEST_MSG, bfloat, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane()
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/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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H A D | bf16_vstN_lane_1.c | 46 VECT_VAR_DECL(expected_st4_2,hbfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable 47 VECT_VAR_DECL(expected_st4_2,hbfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable 211 CHECK_FP(TEST_MSG, bfloat, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 212 CHECK_FP(TEST_MSG, bfloat, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane()
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/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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H A D | bf16_vstN_lane_1.c | 46 VECT_VAR_DECL(expected_st4_2,hbfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable 47 VECT_VAR_DECL(expected_st4_2,hbfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable 211 CHECK_FP(TEST_MSG, bfloat, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 212 CHECK_FP(TEST_MSG, bfloat, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane()
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/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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H A D | bf16_vstN_lane_1.c | 46 VECT_VAR_DECL(expected_st4_2,hbfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable 47 VECT_VAR_DECL(expected_st4_2,hbfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable 211 CHECK_FP(TEST_MSG, bfloat, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 212 CHECK_FP(TEST_MSG, bfloat, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane()
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/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vstX_lane.c | 199 VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 }; variable 203 VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 }; variable 208 VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 }; variable 634 CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 635 CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 636 CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 637 CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT); in exec_vstX_lane() 638 CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 639 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT); in exec_vstX_lane() 643 CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() [all …]
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H A D | bf16_vstN_lane_1.c | 46 VECT_VAR_DECL(expected_st4_2,hbfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable 47 VECT_VAR_DECL(expected_st4_2,hbfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable 211 CHECK_FP(TEST_MSG, bfloat, 16, 4, PRIx16, expected_st4_2, CMT); in exec_vstX_lane() 212 CHECK_FP(TEST_MSG, bfloat, 16, 8, PRIx16, expected_st4_2, CMT); in exec_vstX_lane()
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