| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/proof/ssw/ |
| H A D | sswCore.c | 61 p->fLatchCorr = 0; // performs register correspondence in Ssw_ManSetDefaultParams()
251 if ( !p->pPars->fLatchCorr || p->pPars->nFramesK > 1 ) in Ssw_SignalCorrespondenceRefine()
437 pPars->fLatchCorr = 1; in Ssw_SignalCorrespondence()
472 p->ppClasses = Ssw_ClassesPrepareSimple( pAig, pPars->fLatchCorr, pPars->nMaxLevs ); in Ssw_SignalCorrespondence()
488 …p->ppClasses = Ssw_ClassesPrepare( pAig, pPars->nFramesK, pPars->fLatchCorr, pPars->fConstCorr, pP… in Ssw_SignalCorrespondence()
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| H A D | sswInt.h | 222 extern Ssw_Cla_t * Ssw_ClassesPrepare( Aig_Man_t * pAig, int nFramesK, int fLatchCorr, int fConst…
223 extern Ssw_Cla_t * Ssw_ClassesPrepareSimple( Aig_Man_t * pAig, int fLatchCorr, int nMaxLevs );
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| H A D | ssw.h | 59 int fLatchCorr; // perform register correspondence member
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| H A D | sswClass.c | 596 Ssw_Cla_t * Ssw_ClassesPrepare( Aig_Man_t * pAig, int nFramesK, int fLatchCorr, int fConstCorr, int… in Ssw_ClassesPrepare() argument
639 if ( fLatchCorr ) in Ssw_ClassesPrepare()
724 Ssw_Cla_t * Ssw_ClassesPrepareSimple( Aig_Man_t * pAig, int fLatchCorr, int nMaxLevs ) in Ssw_ClassesPrepareSimple() argument
735 if ( fLatchCorr ) in Ssw_ClassesPrepareSimple()
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| H A D | sswIslands.c | 441 …p->ppClasses = Ssw_ClassesPrepare( pMiter, pPars->nFramesK, pPars->fLatchCorr, pPars->fConstCorr, … in Ssw_SecWithSimilaritySweep()
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/proof/cec/ |
| H A D | cec.h | 71 int fLatchCorr; // consider only latch outputs member
146 int fLatchCorr; // consider only latch outputs member
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| H A D | cecCorr.c | 786 pParsSim->fLatchCorr = pPars->fLatchCorr; in Cec_ManLSCorrespondenceBmc()
798 …pSrm = Gia_ManCorrSpecReduceInit( pAig, pPars->nFrames, nPrefs, !pPars->fLatchCorr, &vOutputs, pPa… in Cec_ManLSCorrespondenceBmc()
936 pParsSim->fLatchCorr = pPars->fLatchCorr; in Cec_ManLSCorrespondenceClasses()
957 pPars->nBTLimit, pPars->nFrames, pPars->fLatchCorr, pPars->fUseRings, pPars->fUseCSat ); in Cec_ManLSCorrespondenceClasses()
961 if ( fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) ) in Cec_ManLSCorrespondenceClasses()
986 …pSrm = Gia_ManCorrSpecReduce( pAig, pPars->nFrames, !pPars->fLatchCorr, &vOutputs, pPars->fUseRing… in Cec_ManLSCorrespondenceClasses()
987 …0 && Gia_ManPiNum(pSrm) == Gia_ManRegNum(pAig)+(pPars->nFrames+!pPars->fLatchCorr)*Gia_ManPiNum(pA… in Cec_ManLSCorrespondenceClasses()
1042 if ( !fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) ) in Cec_ManLSCorrespondenceClasses()
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| H A D | cecSynth.c | 340 pCorPars->fLatchCorr = 1; in Cec_SequentialSynthesisPart()
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| H A D | cecChoice.c | 222 pParsSim->fLatchCorr = 0; in Cec_ManChoiceComputation_int()
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| H A D | cecCore.c | 191 p->fLatchCorr = 0; // consider only latch outputs in Cec_ManCorSetDefaultParams()
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| H A D | cecCec.c | 512 pCorPars->fLatchCorr = 1; in Cec_LatchCorrespondence()
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| H A D | cecClass.c | 862 if ( p->pPars->fLatchCorr ) in Cec_ManSimClassesPrepare()
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/proof/fra/ |
| H A D | fra.h | 84 int fLatchCorr; // computes latch correspondence only member
104 int fLatchCorr; // perform register correspondence member
302 extern void Fra_ClassesPrepare( Fra_Cla_t * p, int fLatchCorr, int nMaxLevs );
331 …Int_t * Fra_ImpDerive( Fra_Man_t * p, int nImpMaxLimit, int nImpUseLimit, int fLatchCorr );
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| H A D | fraImp.c | 154 Vec_Ptr_t * Fra_SmlSortUsingOnes( Fra_Sml_t * p, int fLatchCorr ) in Fra_SmlSortUsingOnes() argument
171 if ( fLatchCorr ) in Fra_SmlSortUsingOnes()
204 if ( fLatchCorr ) in Fra_SmlSortUsingOnes()
321 Vec_Int_t * Fra_ImpDerive( Fra_Man_t * p, int nImpMaxLimit, int nImpUseLimit, int fLatchCorr ) in Fra_ImpDerive() argument
338 vNodes = Fra_SmlSortUsingOnes( pSeq, fLatchCorr ); in Fra_ImpDerive()
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| H A D | fraInd.c | 400 pPars->fLatchCorr = pParams->fLatchCorr; in Fra_FraigInduction()
434 Fra_ClassesPrepare( p->pCla, p->pPars->fLatchCorr, p->pPars->nMaxLevs ); in Fra_FraigInduction()
446 p->pCla->vImps = Fra_ImpDerive( p, 5000000, pPars->nMaxImps, pPars->fLatchCorr ); in Fra_FraigInduction()
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| H A D | fraSec.c | 104 int fLatchCorr = 0; in Fra_FraigSec() local
116 pPars->fLatchCorr = fLatchCorr; in Fra_FraigSec()
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| H A D | fraMan.c | 90 pPars->fLatchCorr = 0; in Fra_ParamsDefaultSeq()
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| H A D | fraClass.c | 276 void Fra_ClassesPrepare( Fra_Cla_t * p, int fLatchCorr, int nMaxLevs ) in Fra_ClassesPrepare() argument
292 if ( fLatchCorr ) in Fra_ClassesPrepare()
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| H A D | fraCore.c | 323 if ( p->pPars->fLatchCorr ) in Fra_FraigSweep()
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| H A D | fraSim.c | 749 Fra_ClassesPrepare( p->pCla, p->pPars->fLatchCorr, 0 ); in Fra_SmlSimulate()
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/proof/dch/ |
| H A D | dchInt.h | 137 extern void Dch_ClassesPrepare( Dch_Cla_t * p, int fLatchCorr, int nMaxLevs );
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| H A D | dchClass.c | 336 void Dch_ClassesPrepare( Dch_Cla_t * p, int fLatchCorr, int nMaxLevs ) in Dch_ClassesPrepare() argument
351 if ( fLatchCorr ) in Dch_ClassesPrepare()
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/abci/ |
| H A D | abc.c | 21206 pPars->fLatchCorr = 0; in Abc_CommandSeqSweep()
21292 pPars->fLatchCorr ^= 1; in Abc_CommandSeqSweep()
21361 …, "\t-l : toggle latch correspondence only [default = %s]\n", pPars->fLatchCorr? "yes": "no" ); in Abc_CommandSeqSweep()
21518 pPars->fLatchCorr ^= 1; in Abc_CommandSeqSweep2()
21645 … "\t-l : toggle doing latch correspondence [default = %s]\n", pPars->fLatchCorr? "yes": "no" ); in Abc_CommandSeqSweep2()
21689 pPars->fLatchCorr = 0; in Abc_CommandTestSeqSweep()
21775 pPars->fLatchCorr ^= 1; in Abc_CommandTestSeqSweep()
21814 …, "\t-l : toggle latch correspondence only [default = %s]\n", pPars->fLatchCorr? "yes": "no" ); in Abc_CommandTestSeqSweep()
35369 pPars->fLatchCorr = 1; in Abc_CommandAbc9Lcorr()
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