1 /*
2 * Copyright (c) 2020-2021, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_avp_cmdpar.h
24 //! \brief MHW command parameters
25 //! \details
26 //!
27
28 #ifndef __MHW_VDBOX_AVP_CMDPAR_H__
29 #define __MHW_VDBOX_AVP_CMDPAR_H__
30
31 #include "codec_def_common_encode.h"
32 #include "codec_def_common_av1.h"
33 #include "mhw_vdbox.h"
34 #include "mhw_vdbox_cmdpar.h"
35
36 #ifdef IGFX_AVP_INTERFACE_EXT_SUPPORT
37 #include "mhw_vdbox_avp_cmdpar_ext.h"
38 #define __MHW_VDBOX_AVP_WRAPPER(STUFF)
39 #define __MHW_VDBOX_AVP_WRAPPER_EXT(STUFF) STUFF
40 #else
41 #define __MHW_VDBOX_AVP_WRAPPER(STUFF) STUFF
42 #define __MHW_VDBOX_AVP_WRAPPER_EXT(STUFF)
43 #endif
44
45 namespace mhw
46 {
47 namespace vdbox
48 {
49 namespace avp
50 {
51
52 enum class SURFACE_FORMAT
53 {
54 SURFACE_FORMAT_P010VARIANT = 3,
55 SURFACE_FORMAT_PLANAR4208 = 4,
56 SURFACE_FORMAT_P010 = 13,
57 };
58
59 enum AvpBufferType
60 {
61 segmentIdBuffer = 0, //!< segment ID temporal buffers
62 mvTemporalBuffer, //!< MV temporal buffers of both current and collocated
63 bsdLineBuffer, //!< bitstream decode line buffer
64 bsdTileLineBuffer, //!< bitstream decode tile line buffer
65 intraPredLineBuffer, //!< intra prediction line buffer
66 intraPredTileLineBuffer,
67 spatialMvLineBuffer,
68 spatialMvTileLineBuffer,
69 lrMetaTileColBuffer, //!< Loop Restoration Meta Tile Column Read/Write Buffer Address
70 lrTileLineYBuffer, //!< Loop Restoration Filter Tile Read/Write Line Y Buffer Address
71 lrTileLineUBuffer, //!< Loop Restoration Filter Tile Read/Write Line U Buffer Address
72 lrTileLineVBuffer, //!< Loop Restoration Filter Tile Read/Write Line V Buffer Address
73 deblockLineYBuffer,
74 deblockLineUBuffer,
75 deblockLineVBuffer,
76 deblockTileLineYBuffer,
77 deblockTileLineVBuffer,
78 deblockTileLineUBuffer,
79 deblockTileColYBuffer,
80 deblockTileColUBuffer,
81 deblockTileColVBuffer,
82 cdefLineBuffer,
83 cdefTileLineBuffer,
84 cdefTileColBuffer,
85 cdefMetaTileLineBuffer,
86 cdefMetaTileColBuffer,
87 cdefTopLeftCornerBuffer,
88 superResTileColYBuffer,
89 superResTileColUBuffer,
90 superResTileColVBuffer,
91 lrTileColYBuffer,
92 lrTileColUBuffer,
93 lrTileColVBuffer,
94 frameStatusErrBuffer,
95 dbdStreamoutBuffer,
96 fgTileColBuffer,
97 fgSampleTmpBuffer,
98 lrTileColAlignBuffer,
99 tileSzStreamOutBuffer,
100 tileStatStreamOutBuffer,
101 cuStreamoutBuffer,
102 sseLineBuffer,
103 sseTileLineBuffer,
104 avpInternalBufferMax
105 };
106
107 enum CommandsNumberOfAddress
108 {
109 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
110 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
111 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
112 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
113 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
114 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 4, // 4 DW for 2 address fields
115 MI_SEMAPHORE_WAIT_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address fields
116 MI_ATOMIC_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
117
118 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
119
120 AVP_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
121 AVP_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
122 AVP_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 61, // 61 address fields
123 AVP_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 3, // 3 address fields
124 AVP_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
125 AVP_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
126 AVP_SEGMENT_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
127 AVP_TILE_CODING_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
128 AVP_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
129 AVP_INLOOP_FILTER_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
130 AVP_INTER_PRED_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
131 AVP_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
132 VDENC_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 12, // 12 DW for 12 address fields
133 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields
134 AVP_FILM_GRAIN_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields
135 };
136
137 struct AvpBufferSizePar
138 {
139 uint8_t bitDepthIdc;
140 uint32_t width;
141 uint32_t height;
142 uint32_t tileWidth;
143 uint32_t bufferSize;
144 bool isSb128x128;
145 uint32_t curFrameTileNum;
146 uint32_t numTileCol;
147 uint8_t numOfActivePipes;
148 };
149
_MHW_PAR_T(AVP_PIPE_MODE_SELECT)150 struct _MHW_PAR_T(AVP_PIPE_MODE_SELECT)
151 {
152 uint8_t codecSelect = 0;
153 bool cdefOutputStreamoutEnableFlag = false;
154 bool lrOutputStreamoutEnableFlag = false;
155 bool picStatusErrorReportEnable = false;
156 uint8_t codecStandardSelect = 0;
157 MHW_VDBOX_HCP_MULTI_ENGINE_MODE multiEngineMode = MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY;
158 MHW_VDBOX_HCP_PIPE_WORK_MODE pipeWorkingMode = MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY;
159 bool tileBasedReplayMode = false;
160 bool picStatusErrorReportId = false;
161 uint8_t phaseIndicator = 0;
162 bool frameReconDisable = false;
163 bool vdencMode = false;
164 bool tileStatsStreamoutEnable = false;
165 bool motionCompMemTrackerCounterEnable = false;
166 bool pakFrameLevelStreamOutEnable = false;
167 bool motionCompMemoryTrackerCntEnable = false;
168 uint8_t srcPixelPrefetchLen = 0;
169 bool srcPixelPrefetchEnable = false;
170 bool sseEnable = false;
171 };
172
_MHW_PAR_T(AVP_PIC_STATE)173 struct _MHW_PAR_T(AVP_PIC_STATE)
174 {
175 uint32_t frameWidthMinus1 = 0;
176 uint32_t frameHeightMinus1 = 0;
177
178 uint8_t frameType = 0;
179 uint8_t primaryRefFrame = 0;
180 bool applyFilmGrainFlag = 0;
181 bool deltaQPresentFlag = false;
182 uint8_t log2DeltaQRes = 0;
183 bool codedLossless = false;
184 uint16_t baseQindex = 0;
185 int8_t yDcDeltaQ = 0;
186 int8_t uDcDeltaQ = 0;
187 int8_t uAcDeltaQ = 0;
188 int8_t vDcDeltaQ = 0;
189 int8_t vAcDeltaQ = 0;
190 bool allowHighPrecisionMV = false;
191 bool referenceSelect = false;
192 uint8_t interpFilter = 0;
193 uint16_t currentOrderHint = 0;
194 bool reducedTxSetUsed = false;
195 uint8_t txMode = 0;
196 bool skipModePresent = false;
197 uint8_t globalMotionType[7] = {};
198 uint8_t refFrameIdx[8] = {};
199
200 CodecAv1SegmentsParams segmentParams = {};
201
202 uint8_t bitDepthIdc = 0;
203 uint8_t chromaFormat = 0;
204 uint32_t superblockSizeUsed = 0;
205 uint8_t skipModeFrame[2] = {};
206 uint8_t refFrameSide = 0;
207 uint8_t refFrameBiasFlag = 0;
208 uint8_t frameLevelGlobalMotionInvalidFlags = 0;
209 uint32_t warpParamsArrayProjection[21] = {};
210 uint32_t refFrameRes[8] = {};
211 uint32_t refScaleFactor[8] = {};
212 uint8_t refOrderHints[8] = {};
213 uint32_t errorResilientMode = 0;
214
215 bool enableOrderHint = false;
216 bool enableCDEF = false;
217 bool enableSuperres = false;
218 bool enableRestoration = false;
219 bool enableFilterIntra = false;
220 bool enableIntraEdgeFilter = false;
221 bool enableDualFilter = false;
222 bool enableInterIntraCompound = false;
223 bool enableMaskedCompound = false;
224 bool enableJointCompound = false;
225 bool forceIntegerMv = false;
226 bool allowWarpedMotion = false;
227 bool enableLargeScaleTile = false;
228 bool motionModeSwitchable = false;
229 bool useReferenceFrameMvSet = false;
230
231 uint8_t orderHintBitsMinus1 = 0;
232
233 bool notFirstPass = false;
234 bool vdencPackOnlyPass = false;
235 bool frameBitRateMaxReportMask = false;
236 bool frameBitRateMinReportMask = false;
237 bool headerPresent = false;
238
239 uint32_t frameBitRateMax = 0;
240 uint32_t frameBitRateMaxUnit = 0; // select unit - 0 : 32B, 1 : 4KB
241 uint32_t frameBitRateMin = 0;
242 uint32_t frameBitRateMinUnit = 0; // select unit - 0 : 32B, 1 : 4KB
243
244 uint32_t frameDeltaQindexMax[2] = {};
245 uint32_t frameDeltaQindexMin = 0;
246
247 uint32_t frameDeltaLFMax[2] = {};
248 uint32_t frameDeltaLFMin = 0;
249
250 uint32_t frameDeltaQindexLFMaxRange[2] = {};
251 uint32_t frameDeltaQindexLFMinRange = 0;
252
253 uint32_t minFramSize = 0;
254 uint32_t minFramSizeUnits = 0;
255
256 uint32_t bitOffsetForFirstPartitionSize = 0;
257
258 uint32_t class0_SSE_Threshold0 = 0;
259 uint32_t class0_SSE_Threshold1 = 0;
260
261 uint32_t rdmult = 0;
262
263 int32_t sbMaxBitSizeAllowed = 0;
264 bool sbMaxSizeReportMask = false;
265
266 bool autoBistreamStitchingInHardware = false;
267
268 bool postCdefPixelStreamoutEn = false;
269
270 bool allowScreenContentTools = false;
271 bool allowIntraBC = false;
272
273 __MHW_VDBOX_AVP_WRAPPER_EXT(AVP_PIC_STATE_CMDPAR_EXT);
274 };
275
_MHW_PAR_T(AVP_INLOOP_FILTER_STATE)276 struct _MHW_PAR_T(AVP_INLOOP_FILTER_STATE)
277 {
278 uint8_t loopFilterLevel[4] = {};
279 uint8_t loopFilterSharpness = 0;
280 bool loopFilterDeltaEnabled = 0;
281 uint8_t deltaLfRes = 0;
282 uint8_t deltaLfMulti = 0;
283 bool loopFilterDeltaUpdate = false;
284
285 int8_t loopFilterRefDeltas[8] = {};
286 int8_t loopFilterModeDeltas[2] = {};
287
288 uint8_t cdefYStrength[8] = {};
289 uint8_t cdefUVStrength[8] = {};
290 uint8_t cdefBits = 0;
291 uint8_t cdefDampingMinus3 = 0;
292
293 //super-resolution;
294 uint32_t superresUpscaledWidthMinus1 = 0;
295 uint8_t superresDenom = 0;
296 int32_t lumaPlaneXStepQn = 0;
297 int32_t lumaPlaneX0Qn = 0;
298 int32_t chromaPlaneXStepQn = 0;
299 int32_t chromaPlaneX0Qn = 0;
300
301 //loop restoration;
302 uint8_t LoopRestorationType[3] = {};
303 uint8_t LoopRestorationSizeLuma = 0;
304 bool UseSameLoopRestorationSizeForChroma = false;
305 };
306
_MHW_PAR_T(AVP_TILE_CODING)307 struct _MHW_PAR_T(AVP_TILE_CODING)
308 {
309 uint16_t tileId = 0;
310 uint16_t tileNum = 0; //!< Tile ID in its Tile group
311 uint16_t tileGroupId = 0;
312
313 uint16_t tileColPositionInSb = 0;
314 uint16_t tileRowPositionInSb = 0;
315
316 uint16_t tileWidthInSbMinus1 = 0; //!< Tile width minus 1 in SB unit
317 uint16_t tileHeightInSbMinus1 = 0; //!< Tile height minus 1 in SB unit
318
319 bool tileRowIndependentFlag = false;
320 bool firstTileInAFrame = false;
321 bool lastTileOfColumn = false;
322 bool lastTileOfRow = false;
323 bool firstTileOfTileGroup = false;
324 bool lastTileOfTileGroup = false;
325 bool lastTileOfFrame = false;
326 bool disableCdfUpdateFlag = false;
327 bool disableFrameContextUpdateFlag = false;
328
329 uint8_t numOfActiveBePipes = 0;
330 uint16_t numOfTileColumnsInFrame = 0;
331 uint16_t numOfTileRowsInFrame = 0;
332 uint16_t outputDecodedTileColPos = 0;
333 uint16_t outputDecodedTileRowPos = 0;
334 };
335
_MHW_PAR_T(AVP_SEGMENT_STATE)336 struct _MHW_PAR_T(AVP_SEGMENT_STATE)
337 {
338 uint8_t numSegments = 1;
339 CodecAv1SegmentsParams av1SegmentParams = {};
340 uint8_t currentSegmentId = 0;
341 };
342
_MHW_PAR_T(AVP_PIPE_BUF_ADDR_STATE)343 struct _MHW_PAR_T(AVP_PIPE_BUF_ADDR_STATE)
344 {
345 PMOS_RESOURCE refs[8] = {};
346 MOS_MEMCOMP_STATE mmcStatePreDeblock = MOS_MEMCOMP_DISABLED;
347 MOS_MEMCOMP_STATE mmcStateRawSurf = MOS_MEMCOMP_DISABLED;
348 PMOS_SURFACE decodedPic = nullptr;
349 PMOS_RESOURCE intrabcDecodedOutputFrameBuffer = nullptr;
350 PMOS_RESOURCE cdfTableInitBuffer = nullptr;
351 uint32_t cdfTableInitBufferOffset = 0;
352 PMOS_RESOURCE cdfTableBwdAdaptBuffer = nullptr;
353 PMOS_RESOURCE segmentIdReadBuffer = nullptr;
354 PMOS_RESOURCE segmentIdWriteBuffer = nullptr;
355 PMOS_RESOURCE colMvTempBuffer[9] = {};
356 PMOS_RESOURCE curMvTempBuffer = nullptr;
357 PMOS_RESOURCE bsLineRowstoreBuffer = nullptr;
358 PMOS_RESOURCE bsTileLineRowstoreBuffer = nullptr;
359 PMOS_RESOURCE intraPredLineRowstoreBuffer = nullptr;
360 PMOS_RESOURCE intraPredTileLineRowstoreBuffer = nullptr;
361 PMOS_RESOURCE spatialMVLineBuffer = nullptr;
362 PMOS_RESOURCE spatialMVCodingTileLineBuffer = nullptr;
363 PMOS_RESOURCE lrMetaTileColumnBuffer = nullptr;
364 PMOS_RESOURCE lrTileLineYBuffer = nullptr;
365 PMOS_RESOURCE lrTileLineUBuffer = nullptr;
366 PMOS_RESOURCE lrTileLineVBuffer = nullptr;
367 PMOS_RESOURCE deblockLineYBuffer = nullptr;
368 PMOS_RESOURCE deblockLineUBuffer = nullptr;
369 PMOS_RESOURCE deblockLineVBuffer = nullptr;
370 PMOS_RESOURCE deblockTileLineYBuffer = nullptr;
371 PMOS_RESOURCE deblockTileLineVBuffer = nullptr;
372 PMOS_RESOURCE deblockTileLineUBuffer = nullptr;
373 PMOS_RESOURCE deblockTileColumnYBuffer = nullptr;
374 PMOS_RESOURCE deblockTileColumnUBuffer = nullptr;
375 PMOS_RESOURCE deblockTileColumnVBuffer = nullptr;
376 PMOS_RESOURCE cdefLineBuffer = nullptr;
377 PMOS_RESOURCE cdefTileLineBuffer = nullptr;
378 PMOS_RESOURCE cdefTileColumnBuffer = nullptr;
379 PMOS_RESOURCE cdefMetaTileLineBuffer = nullptr;
380 PMOS_RESOURCE cdefMetaTileColumnBuffer = nullptr;
381 PMOS_RESOURCE cdefTopLeftCornerBuffer = nullptr;
382 PMOS_RESOURCE superResTileColumnYBuffer = nullptr;
383 PMOS_RESOURCE superResTileColumnUBuffer = nullptr;
384 PMOS_RESOURCE superResTileColumnVBuffer = nullptr;
385 PMOS_RESOURCE lrTileColumnYBuffer = nullptr;
386 PMOS_RESOURCE lrTileColumnUBuffer = nullptr;
387 PMOS_RESOURCE lrTileColumnVBuffer = nullptr;
388 PMOS_RESOURCE lrTileColumnAlignBuffer = nullptr;
389 PMOS_RESOURCE decodedFrameStatusErrorBuffer = nullptr;
390 PMOS_RESOURCE decodedBlockDataStreamoutBuffer = nullptr;
391 PMOS_RESOURCE originalPicSourceBuffer = nullptr;
392 PMOS_RESOURCE dsPictureSourceBuffer = nullptr;
393 PMOS_RESOURCE tileSizeStreamoutBuffer = nullptr;
394 uint32_t tileSizeStreamoutBufferOffset = 0;
395 PMOS_RESOURCE tileStatisticsPakStreamoutBuffer = nullptr;
396 PMOS_RESOURCE cuStreamoutBuffer = nullptr;
397 PMOS_RESOURCE sseLineBuffer = nullptr;
398 PMOS_RESOURCE sseTileLineBuffer = nullptr;
399 PMOS_SURFACE postCDEFpixelsBuffer = nullptr;
400 MOS_MEMCOMP_STATE postCdefSurfMmcState = MOS_MEMCOMP_DISABLED;
401
402 PMOS_RESOURCE filmGrainTileColumnDataBuffer = nullptr;
403 PMOS_RESOURCE filmGrainSampleTemplateBuffer = nullptr;
404 PMOS_RESOURCE filmGrainOutputSurface = nullptr;
405
406 PMOS_RESOURCE rhoDomainThresholdTableBuffer = nullptr;
407 };
408
_MHW_PAR_T(AVP_INTER_PRED_STATE)409 struct _MHW_PAR_T(AVP_INTER_PRED_STATE)
410 {
411 uint8_t savedRefOrderHints[7][7];
412 uint8_t refMaskMfProj;
413 };
414
_MHW_PAR_T(AVP_IND_OBJ_BASE_ADDR_STATE)415 struct _MHW_PAR_T(AVP_IND_OBJ_BASE_ADDR_STATE)
416 {
417 uint32_t Mode = 0;
418 PMOS_RESOURCE dataBuffer = nullptr;
419 uint32_t dataSize = 0;
420 uint32_t dataOffset = 0;
421 PMOS_RESOURCE mvObjectBuffer = nullptr;
422 uint32_t mvObjectSize = 0;
423 uint32_t mvObjectOffset = 0;
424 PMOS_RESOURCE pakBaseObjectBuffer = nullptr;
425 uint32_t pakBaseObjectSize = 0;
426 uint32_t pakBaseObjectOffset = 0;
427 PMOS_RESOURCE pakTileSizeStasBuffer = nullptr;
428 uint32_t pakTileSizeStasBufferSize = 0;
429 uint32_t pakTileSizeRecordOffset = 0;
430 };
431
_MHW_PAR_T(AVP_SURFACE_STATE)432 struct _MHW_PAR_T(AVP_SURFACE_STATE)
433 {
434 uint32_t pitch = 0;
435 uint32_t uOffset = 0;
436 uint32_t vOffset = 0;
437 uint8_t surfaceStateId = 0;
438 uint8_t bitDepthLumaMinus8 = 0;
439 MOS_MEMCOMP_STATE mmcState = MOS_MEMCOMP_DISABLED;
440 uint32_t compressionFormat = 0;
441 SURFACE_FORMAT srcFormat = SURFACE_FORMAT::SURFACE_FORMAT_PLANAR4208;
442 uint32_t uvPlaneAlignment = 0;
443 };
444
_MHW_PAR_T(AVP_BSD_OBJECT)445 struct _MHW_PAR_T(AVP_BSD_OBJECT)
446 {
447 uint32_t bsdDataLength = 0;
448 uint32_t bsdDataStartOffset = 0;
449 };
450
_MHW_PAR_T(AVP_PAK_INSERT_OBJECT)451 struct _MHW_PAR_T(AVP_PAK_INSERT_OBJECT)
452 {
453 PBSBuffer bsBuffer = nullptr;
454 // also reuse dwBitSize for passing SrcDataEndingBitInclusion when (pEncoder->bLastPicInStream || pEncoder->bLastPicInSeq)
455 uint32_t bitSize = 0;
456 uint32_t offset = 0;
457 uint32_t skipEmulationCheckCount = 0;
458 bool lastPicInSeq = false;
459 bool lastPicInStream = false;
460 bool lastHeader = false;
461 bool emulationByteBitsInsert = false;
462 bool setLastPicInStreamData = false;
463 bool sliceHeaderIndicator = false;
464 bool headerLengthExcludeFrmSize = false;
465 bool bResetBitstreamStartingPos = false;
466 bool endOfHeaderInsertion = false;
467 uint32_t lastPicInSeqData = 0;
468 uint32_t lastPicInStreamData = 0;
469 PMHW_BATCH_BUFFER batchBufferForPakSlices = nullptr;
470 };
471
_MHW_PAR_T(AVP_CMD1)472 struct _MHW_PAR_T(AVP_CMD1)
473 {
474 __MHW_VDBOX_AVP_WRAPPER_EXT(AVP_CMD1_CMDPAR_EXT);
475 };
476
477 } // namespace avp
478 } // namespace vdbox
479 } // namespace mhw
480
481 #endif // __MHW_VDBOX_AVP_CMDPAR_H__
482