| /dports/cad/yosys/yosys-yosys-0.12/passes/cmds/ |
| H A D | delete.cc | 46 bool flag_output = false; in execute() local
56 flag_output = true; in execute()
61 flag_output = true; in execute()
71 if (design->selected_whole_module(module->name) && !flag_input && !flag_output) { in execute()
79 if (flag_input || flag_output) { in execute()
84 if (flag_output) in execute()
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| H A D | rename.cc | 27 …name_in_module(RTLIL::Module *module, std::string from_name, std::string to_name, bool flag_output) in rename_in_module() argument
41 if (wire_to_rename->port_id || flag_output) { in rename_in_module()
42 if (flag_output) in rename_in_module()
50 if (flag_output) in rename_in_module()
163 bool flag_output = false; in execute() local
176 flag_output = true; in execute()
333 … rename_in_module(design->module(design->selected_active_module), from_name, to_name, flag_output); in execute()
337 if (flag_output) in execute()
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| H A D | add.cc | 61 …IL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_glob… in add_wire() argument
76 if (wire != nullptr && wire->port_output != flag_output) in add_wire()
88 wire->port_output = flag_output; in add_wire()
90 if (flag_input || flag_output) { in add_wire()
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| H A D | setundef.cc | 36 …e * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output) in add_wire() argument
45 return add_wire(module, name, width, flag_input, flag_output); in add_wire()
51 wire->port_output = flag_output; in add_wire()
53 if (flag_input || flag_output) { in add_wire()
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| /dports/textproc/xsv-rs/xsv-0.13.0/src/cmd/ |
| H A D | cat.rs | 47 flag_output: Option<String>, field
73 let mut wtr = Config::new(&self.flag_output).writer()?; in cat_rows()
87 let mut wtr = Config::new(&self.flag_output).writer()?; in cat_columns()
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| H A D | index.rs | 40 flag_output: Option<String>, field
47 let pidx = match args.flag_output { in run()
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| H A D | select.rs | 54 flag_output: Option<String>, field
68 let mut wtr = Config::new(&args.flag_output).writer()?; in run()
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| H A D | input.rs | 34 flag_output: Option<String>, field
47 let wconfig = Config::new(&args.flag_output); in run()
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| H A D | table.rs | 44 flag_output: Option<String>, field
54 let wconfig = Config::new(&args.flag_output) in run()
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| H A D | fixlengths.rs | 40 flag_output: Option<String>, field
81 let mut wtr = Config::new(&args.flag_output).writer()?; in run()
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| H A D | fmt.rs | 42 flag_output: Option<String>, field
55 let mut wconfig = Config::new(&args.flag_output) in run()
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| H A D | search.rs | 43 flag_output: Option<String>, field
61 let mut wtr = Config::new(&args.flag_output).writer()?; in run()
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| H A D | slice.rs | 51 flag_output: Option<String>, field
108 Config::new(&self.flag_output) in wconfig()
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| H A D | sample.rs | 45 flag_output: Option<String>, field
57 let mut wtr = Config::new(&args.flag_output).writer()?; in run()
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| H A D | sort.rs | 42 flag_output: Option<String>, field
89 let mut wtr = Config::new(&args.flag_output).writer()?; in run()
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| H A D | frequency.rs | 71 flag_output: Option<String>, field
80 let mut wtr = Config::new(&args.flag_output).writer()?; in run()
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| H A D | join.rs | 86 flag_output: Option<String>, field
296 wtr: Config::new(&self.flag_output).writer()?, in new_io_state()
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| H A D | stats.rs | 80 flag_output: Option<String>, field
88 let mut wtr = Config::new(&args.flag_output).writer()?; in run()
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| /dports/devel/py-tables/tables-3.6.1/ |
| H A D | cpuinfo.py | 2026 returncode, flag_output = DataSource.isainfo_vb()
2027 if flag_output == None or returncode != 0:
2043 flags = flag_output.strip().split('\n')[-1].strip().lower().split()
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| /dports/sysutils/py-py-cpuinfo/py-cpuinfo-8.0.0/cpuinfo/ |
| H A D | cpuinfo.py | 2536 returncode, flag_output = DataSource.isainfo_vb()
2537 if flag_output == None or returncode != 0:
2555 flags = flag_output.strip().split('\n')[-1].strip().lower().split()
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