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Searched refs:fmul_s (Results 1 – 25 of 153) sorted by relevance

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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/RISCV/
H A Dfloat-arith.ll29 define float @fmul_s(float %a, float %b) nounwind {
30 ; RV32IF-LABEL: fmul_s:
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/
H A Dsve-fp.ll59 define <vscale x 4 x float> @fmul_s(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
60 ; CHECK-LABEL: fmul_s:
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/
H A Dsve-fp.ll59 define <vscale x 4 x float> @fmul_s(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
60 ; CHECK-LABEL: fmul_s:
/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/
H A Dhelper.h20 DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
H A Dinsn32.decode160 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/
H A Dhelper.h20 DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
H A Dinsn32.decode164 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
/dports/emulators/qemu42/qemu-4.2.1/target/riscv/
H A Dhelper.h20 DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
H A Dinsn32.decode160 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/riscv/
H A Dhelper.h20 DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/
H A Dhelper.h20 DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/RISCV/
H A Dhalf-arith.ll41 define half @fmul_s(half %a, half %b) nounwind {
42 ; RV32IZFH-LABEL: fmul_s:
47 ; RV64IZFH-LABEL: fmul_s:
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dhalf-arith.ll41 define half @fmul_s(half %a, half %b) nounwind {
42 ; RV32IZFH-LABEL: fmul_s:
47 ; RV64IZFH-LABEL: fmul_s:
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/RISCV/
H A Dhalf-arith.ll41 define half @fmul_s(half %a, half %b) nounwind {
42 ; RV32IZFH-LABEL: fmul_s:
47 ; RV64IZFH-LABEL: fmul_s:
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/
H A Dhalf-arith.ll41 define half @fmul_s(half %a, half %b) nounwind {
42 ; RV32IZFH-LABEL: fmul_s:
47 ; RV64IZFH-LABEL: fmul_s:
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dhalf-arith.ll41 define half @fmul_s(half %a, half %b) nounwind {
42 ; RV32IZFH-LABEL: fmul_s:
47 ; RV64IZFH-LABEL: fmul_s:
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/
H A Dhalf-arith.ll41 define half @fmul_s(half %a, half %b) nounwind {
42 ; RV32IZFH-LABEL: fmul_s:
47 ; RV64IZFH-LABEL: fmul_s:
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dhalf-arith.ll41 define half @fmul_s(half %a, half %b) nounwind {
42 ; RV32IZFH-LABEL: fmul_s:
47 ; RV64IZFH-LABEL: fmul_s:
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/RISCV/
H A Dfloat-arith.ll33 define float @fmul_s(float %a, float %b) nounwind {
34 ; RV32IF-LABEL: fmul_s:
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/RISCV/
H A Dfloat-arith.ll51 define float @fmul_s(float %a, float %b) nounwind {
52 ; RV32IF-LABEL: fmul_s:
60 ; RV64IF-LABEL: fmul_s:
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/RISCV/
H A Dfloat-arith.ll51 define float @fmul_s(float %a, float %b) nounwind {
52 ; RV32IF-LABEL: fmul_s:
60 ; RV64IF-LABEL: fmul_s:
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/RISCV/
H A Dfloat-arith.ll51 define float @fmul_s(float %a, float %b) nounwind {
52 ; RV32IF-LABEL: fmul_s:
60 ; RV64IF-LABEL: fmul_s:
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/RISCV/
H A Dfloat-arith.ll51 define float @fmul_s(float %a, float %b) nounwind {
52 ; RV32IF-LABEL: fmul_s:
60 ; RV64IF-LABEL: fmul_s:
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/RISCV/
H A Dfloat-arith.ll51 define float @fmul_s(float %a, float %b) nounwind {
52 ; RV32IF-LABEL: fmul_s:
60 ; RV64IF-LABEL: fmul_s:
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/RISCV/
H A Dfloat-arith.ll51 define float @fmul_s(float %a, float %b) nounwind {
52 ; RV32IF-LABEL: fmul_s:
60 ; RV64IF-LABEL: fmul_s:

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