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Searched +refs:fp +refs:reg +refs:type (Results 1 – 25 of 6980) sorted by relevance

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/dports/net/freerdp/freerdp-2.5.0/winpr/libwinpr/registry/
H A Dregistry_reg.c99 WINPR_ASSERT(reg->fp); in reg_load_start()
101 _fseeki64(reg->fp, 0, SEEK_END); in reg_load_start()
102 file_size = _ftelli64(reg->fp); in reg_load_start()
103 _fseeki64(reg->fp, 0, SEEK_SET); in reg_load_start()
488 reg->fp = winpr_fopen(reg->filename, "r"); in reg_open()
491 reg->fp = winpr_fopen(reg->filename, "r+"); in reg_open()
493 if (!reg->fp) in reg_open()
494 reg->fp = winpr_fopen(reg->filename, "w+"); in reg_open()
497 if (!reg->fp) in reg_open()
521 if (reg->fp) in reg_close()
[all …]
/dports/cad/gmsh/gmsh-4.9.2-source/Geo/
H A DGModelIO_ACTRAN.cpp35 if(!fp) { in readACTRAN()
42 fclose(fp); in readACTRAN()
48 fclose(fp); in readACTRAN()
87 int num, type, reg, n[8]; in readACTRAN() local
88 sscanf(buffer, "%d %d %d", &num, &type, &reg); in readACTRAN()
90 if(type == 2) { in readACTRAN()
91 sscanf(buffer, "%d %d %d %d %d", &num, &type, &reg, &n[0], &n[1]); in readACTRAN()
95 else if(type == 4) { in readACTRAN()
96 sscanf(buffer, "%d %d %d %d %d %d", &num, &type, &reg, &n[0], &n[1], in readACTRAN()
102 sscanf(buffer, "%d %d %d %d %d %d %d", &num, &type, &reg, &n[0], in readACTRAN()
[all …]
H A DGModelIO_DIFF.cpp256 type = MSH_TRI_3; in readDIFF()
262 type = MSH_TRI_6; in readDIFF()
268 type = MSH_QUA_4; in readDIFF()
274 type = MSH_QUA_8; in readDIFF()
280 type = MSH_QUA_9; in readDIFF()
286 type = MSH_TET_4; in readDIFF()
292 type = MSH_TET_10; in readDIFF()
298 type = MSH_HEX_8; in readDIFF()
305 type = MSH_HEX_20; in readDIFF()
313 type = MSH_HEX_27; in readDIFF()
[all …]
/dports/emulators/fs-uae/fs-uae-3.1.35/src/
H A Dfpp.cpp749 if (type == FPU_EXP_UNIMP_INS || type == FPU_EXP_DISABLED) { in fpu_op_unimp()
2485 regs.fp[reg].fp = (float)regs.fp[reg].fp; in fround()
2596 regs.fp[reg].fp = -src; in arithmetic_fp()
2607 regs.fp[reg].fp = 0; in arithmetic_fp()
2618 regs.fp[reg].fp = 0; in arithmetic_fp()
2628 regs.fp[reg].fp /= src; in arithmetic_fp()
2633 regs.fp[reg].fp = regs.fp[reg].fp - quot * src; in arithmetic_fp()
2639 regs.fp[reg].fp += src; in arithmetic_fp()
2644 regs.fp[reg].fp *= src; in arithmetic_fp()
2653 regs.fp[reg].fp = regs.fp[reg].fp - quot * src; in arithmetic_fp()
[all …]
/dports/games/abuse_sdl/abuse-0.8/src/
H A Dloader2.cpp99 delete fp; in use_file()
114 delete fp; in done_file()
125 delete fp; in insert_tiles()
130 if (se->type==SPEC_FORETILE) in insert_tiles()
132 else if (se->type==SPEC_BACKTILE) in insert_tiles()
153 if (sd.entries[i]->type==SPEC_FORETILE) in insert_tiles()
159 if (sd.entries[i]->type==SPEC_BACKTILE) in insert_tiles()
173 bFILE *fp; in load_tiles() local
202 switch (spe->type) in load_tiles()
249 switch (spe->type) in load_tiles()
[all …]
/dports/www/node10/node-v10.24.1/deps/v8/src/wasm/baseline/mips64/
H A Dliftoff-assembler-mips64.h72 inline void push(LiftoffAssembler* assm, LiftoffRegister reg, ValueType type) { in push() argument
80 assm->swc1(reg.fp(), MemOperand(sp, 0)); in push()
84 assm->Sdc1(reg.fp(), MemOperand(sp, 0)); in push()
389 LiftoffRegister reg = GetUnusedRegister(reg_class_for(type)); in MoveStackValue() local
390 Fill(reg, src_index, type); in MoveStackValue()
391 Spill(dst_index, reg, type); in MoveStackValue()
418 swc1(reg.fp(), dst); in Spill()
421 TurboAssembler::Sdc1(reg.fp(), dst); in Spill()
462 lwc1(reg.fp(), src); in Fill()
465 TurboAssembler::Ldc1(reg.fp(), src); in Fill()
[all …]
/dports/www/node10/node-v10.24.1/deps/v8/src/wasm/baseline/mips/
H A Dliftoff-assembler-mips.h90 assm->swc1(reg.fp(), MemOperand(sp, 0)); in push()
94 assm->Sdc1(reg.fp(), MemOperand(sp, 0)); in push()
450 liftoff::Load(this, dst, fp, offset, type); in LoadCallerFrameSlot()
456 LiftoffRegister reg = GetUnusedRegister(reg_class_for(type)); in MoveStackValue() local
457 Fill(reg, src_index, type); in MoveStackValue()
458 Spill(dst_index, reg, type); in MoveStackValue()
485 swc1(reg.fp(), dst); in Spill()
488 TurboAssembler::Sdc1(reg.fp(), dst); in Spill()
536 lwc1(reg.fp(), src); in Fill()
539 TurboAssembler::Ldc1(reg.fp(), src); in Fill()
[all …]
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/compiler/nir/
H A Dnir_print.c84 if (reg->name != NULL) in print_register()
85 fprintf(fp, "/* %s */ ", reg->name); in print_register()
86 fprintf(fp, "r%u", reg->index); in print_register()
98 fprintf(fp, "decl_reg %s %u ", sizes[reg->num_components], reg->bit_size); in print_register_decl()
99 print_register(reg, state); in print_register_decl()
101 fprintf(fp, "[%u]", reg->num_array_elems); in print_register_decl()
232 dest->write_mask != (1 << dest->dest.reg.reg->num_components) - 1) { in print_alu_dest()
233 unsigned live_channels = dest->dest.reg.reg->num_components; in print_alu_dest()
494 fprintf(fp, "%s %s", glsl_get_type_name(var->type), in print_var_decl()
590 fprintf(fp, "(%s *)", glsl_get_type_name(instr->type)); in print_deref_link()
[all …]
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pci/
H A Dsv.c462 arg.type = AUDIODEV_TYPE_OPL; in sv_attach()
995 dip->type = AUDIO_MIXER_CLASS; in sv_query_devinfo()
1013 dip->type = AUDIO_MIXER_VALUE; in sv_query_devinfo()
1024 dip->type = AUDIO_MIXER_ENUM; in sv_query_devinfo()
1045 dip->type = AUDIO_MIXER_ENUM; in sv_query_devinfo()
1060 dip->type = AUDIO_MIXER_VALUE; in sv_query_devinfo()
1078 dip->type = AUDIO_MIXER_ENUM; in sv_query_devinfo()
1179 if (cp->type != AUDIO_MIXER_ENUM) in sv_mixer_set_port()
1231 if (cp->type != AUDIO_MIXER_ENUM) in sv_mixer_set_port()
1392 cp.type = AUDIO_MIXER_ENUM; in sv_init_mixer()
[all …]
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/ic/
H A Dad1848.c655 if (cp->type != AUDIO_MIXER_VALUE) in ad1848_mixer_get_port()
673 if (cp->type != AUDIO_MIXER_ENUM) break; in ad1848_mixer_get_port()
680 if (cp->type != AUDIO_MIXER_VALUE) break; in ad1848_mixer_get_port()
689 if (cp->type != AUDIO_MIXER_VALUE) break; in ad1848_mixer_get_port()
698 if (cp->type != AUDIO_MIXER_ENUM) break; in ad1848_mixer_get_port()
728 if (cp->type != AUDIO_MIXER_VALUE) in ad1848_mixer_set_port()
744 if (cp->type != AUDIO_MIXER_ENUM) break; in ad1848_mixer_set_port()
752 if (cp->type != AUDIO_MIXER_VALUE) break; in ad1848_mixer_set_port()
759 if (cp->type != AUDIO_MIXER_VALUE) break; in ad1848_mixer_set_port()
766 if (cp->type != AUDIO_MIXER_ENUM) break; in ad1848_mixer_set_port()
[all …]
/dports/lang/racket-minimal/racket-8.3/src/ChezScheme/s/
H A Dppc32.ss485 (safe-assert (eq? type 'fp))
1765 (if (eq? (info-condition-code-type info) 'fp<=)
2156 [(fx> fp-reg-count 0)
2171 (move-registers regs fp-reg-count fp-regs #f offset e))
2173 (define (pop-registers regs fp-reg-count fp-regs offset e)
2174 (move-registers regs fp-reg-count fp-regs #t offset e)))
2739 [result-type (info-foreign-result-type info)]
3443 (lambda (result-type return-space-offset int-reg-offset)
3525 [fp-reg-count (length (fp-parameter-regs))])
3526 …values ([(iint iflt) (count-reg-args arg-type* gp-reg-count fp-reg-count (indirect-result-that-fit…
[all …]
/dports/lang/racket/racket-8.3/src/ChezScheme/s/
H A Dppc32.ss485 (safe-assert (eq? type 'fp))
1765 (if (eq? (info-condition-code-type info) 'fp<=)
2156 [(fx> fp-reg-count 0)
2171 (move-registers regs fp-reg-count fp-regs #f offset e))
2173 (define (pop-registers regs fp-reg-count fp-regs offset e)
2174 (move-registers regs fp-reg-count fp-regs #t offset e)))
2739 [result-type (info-foreign-result-type info)]
3443 (lambda (result-type return-space-offset int-reg-offset)
3525 [fp-reg-count (length (fp-parameter-regs))])
3526 …values ([(iint iflt) (count-reg-args arg-type* gp-reg-count fp-reg-count (indirect-result-that-fit…
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dwineh6.mir37 - { reg: '$w0', virtual-reg: '' }
38 - { reg: '$w1', virtual-reg: '' }
39 - { reg: '$w2', virtual-reg: '' }
40 - { reg: '$w3', virtual-reg: '' }
61 - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
65 - { id: 1, name: '', type: default, offset: -24, size: 4, alignment: 4,
69 - { id: 2, name: '', type: default, offset: -28, size: 4, alignment: 4,
73 - { id: 3, name: '', type: default, offset: -32, size: 4, alignment: 4,
77 - { id: 4, name: '', type: default, offset: -40, size: 8, alignment: 8,
81 - { id: 5, name: '', type: variable-sized, offset: -40,
[all …]
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/wasm/baseline/mips/
H A Dliftoff-assembler-mips.h117 assm->swc1(reg.fp(), MemOperand(sp, 0)); in push()
121 assm->Sdc1(reg.fp(), MemOperand(sp, 0)); in push()
590 liftoff::Load(this, dst, fp, offset, type); in LoadCallerFrameSlot()
596 LiftoffRegister reg = GetUnusedRegister(reg_class_for(type)); in MoveStackValue() local
597 Fill(reg, src_offset, type); in MoveStackValue()
598 Spill(dst_offset, reg, type); in MoveStackValue()
624 swc1(reg.fp(), dst); in Spill()
627 TurboAssembler::Sdc1(reg.fp(), dst); in Spill()
674 lwc1(reg.fp(), src); in Fill()
677 TurboAssembler::Ldc1(reg.fp(), src); in Fill()
[all …]
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/compiler/nir/
H A Dnir_print.c85 fprintf(fp, "r%u", reg->index); in print_register()
97 fprintf(fp, "decl_reg %s %u ", sizes[reg->num_components], reg->bit_size); in print_register_decl()
98 print_register(reg, state); in print_register_decl()
99 if (reg->num_array_elems != 0) in print_register_decl()
100 fprintf(fp, "[%u]", reg->num_array_elems); in print_register_decl()
227 dest->write_mask != (1 << dest->dest.reg.reg->num_components) - 1) { in print_alu_dest()
228 unsigned live_channels = dest->dest.reg.reg->num_components; in print_alu_dest()
521 fprintf(fp, "%s %s", glsl_get_type_name(var->type), in print_var_decl()
628 fprintf(fp, "(%s *)", glsl_get_type_name(instr->type)); in print_deref_link()
738 fprintf(fp, " %s) ", glsl_get_type_name(instr->type)); in print_deref_instr()
[all …]
/dports/lang/clover/mesa-21.3.6/src/compiler/nir/
H A Dnir_print.c85 fprintf(fp, "r%u", reg->index); in print_register()
97 fprintf(fp, "decl_reg %s %u ", sizes[reg->num_components], reg->bit_size); in print_register_decl()
98 print_register(reg, state); in print_register_decl()
99 if (reg->num_array_elems != 0) in print_register_decl()
100 fprintf(fp, "[%u]", reg->num_array_elems); in print_register_decl()
227 dest->write_mask != (1 << dest->dest.reg.reg->num_components) - 1) { in print_alu_dest()
228 unsigned live_channels = dest->dest.reg.reg->num_components; in print_alu_dest()
521 fprintf(fp, "%s %s", glsl_get_type_name(var->type), in print_var_decl()
628 fprintf(fp, "(%s *)", glsl_get_type_name(instr->type)); in print_deref_link()
738 fprintf(fp, " %s) ", glsl_get_type_name(instr->type)); in print_deref_instr()
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/compiler/nir/
H A Dnir_print.c85 fprintf(fp, "r%u", reg->index); in print_register()
97 fprintf(fp, "decl_reg %s %u ", sizes[reg->num_components], reg->bit_size); in print_register_decl()
98 print_register(reg, state); in print_register_decl()
99 if (reg->num_array_elems != 0) in print_register_decl()
100 fprintf(fp, "[%u]", reg->num_array_elems); in print_register_decl()
227 dest->write_mask != (1 << dest->dest.reg.reg->num_components) - 1) { in print_alu_dest()
228 unsigned live_channels = dest->dest.reg.reg->num_components; in print_alu_dest()
521 fprintf(fp, "%s %s", glsl_get_type_name(var->type), in print_var_decl()
628 fprintf(fp, "(%s *)", glsl_get_type_name(instr->type)); in print_deref_link()
738 fprintf(fp, " %s) ", glsl_get_type_name(instr->type)); in print_deref_instr()
[all …]

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