| /dports/devel/avr-gdb/gdb-7.3.1/sim/frv/ |
| H A D | frv.c | 826 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_GR()
876 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_FRint()
926 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_CPR()
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| H A D | frv-sim.h | 919 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
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| H A D | memory.c | 1019 frvbf_mem_set_XI (SIM_CPU *current_cpu, IADDR pc, SI address, SI *value) in frvbf_mem_set_XI() function
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| H A D | ChangeLog | 600 (frvbf_mem_set_XI): Ditto.
871 (frvbf_mem_set_XI): Use cycle-accurate cache write if 'model_insn'.
1165 (frvbf_mem_set_XI): Align address.
1680 (frvbf_mem_set_XI): New function.
1723 (frvbf_mem_set_XI): New function.
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| /dports/devel/gdb761/gdb-7.6.1/sim/frv/ |
| H A D | frv.c | 825 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_GR()
875 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_FRint()
925 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_CPR()
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| H A D | frv-sim.h | 918 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
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| H A D | memory.c | 1018 frvbf_mem_set_XI (SIM_CPU *current_cpu, IADDR pc, SI address, SI *value) in frvbf_mem_set_XI() function
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| H A D | ChangeLog | 645 (frvbf_mem_set_XI): Ditto.
916 (frvbf_mem_set_XI): Use cycle-accurate cache write if 'model_insn'.
1210 (frvbf_mem_set_XI): Align address.
1725 (frvbf_mem_set_XI): New function.
1768 (frvbf_mem_set_XI): New function.
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| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/frv/ |
| H A D | frv.c | 827 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_GR()
877 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_FRint()
927 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_CPR()
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| H A D | frv-sim.h | 919 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
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| H A D | memory.c | 1019 frvbf_mem_set_XI (SIM_CPU *current_cpu, IADDR pc, SI address, SI *value) in frvbf_mem_set_XI() function
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| H A D | ChangeLog | 463 (frvbf_mem_set_XI): Ditto.
734 (frvbf_mem_set_XI): Use cycle-accurate cache write if 'model_insn'.
1028 (frvbf_mem_set_XI): Align address.
1543 (frvbf_mem_set_XI): New function.
1586 (frvbf_mem_set_XI): New function.
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| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/frv/ |
| H A D | frv.c | 827 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_GR()
877 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_FRint()
927 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); in frvbf_store_quad_CPR()
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| H A D | frv-sim.h | 919 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
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| H A D | memory.c | 1019 frvbf_mem_set_XI (SIM_CPU *current_cpu, IADDR pc, SI address, SI *value) in frvbf_mem_set_XI() function
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| H A D | ChangeLog | 463 (frvbf_mem_set_XI): Ditto.
734 (frvbf_mem_set_XI): Use cycle-accurate cache write if 'model_insn'.
1028 (frvbf_mem_set_XI): Align address.
1543 (frvbf_mem_set_XI): New function.
1586 (frvbf_mem_set_XI): New function.
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