| /dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/visa/VisaToG4/ |
| H A D | TranslateALU.cpp | 142 phyregpool.getAcc0Reg(), in translateVISAArithmeticInst()
153 phyregpool.getAcc0Reg(), in translateVISAArithmeticInst()
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| H A D | TranslateSendLdStLsc.cpp | 1360 G4_DstRegRegion *dstAcc0 = createDst(phyregpool.getAcc0Reg(), 0, 0, 1, Type_UD); in lscAdd64AosEmu()
1368 createSrc(phyregpool.getAcc0Reg(), 0, 0, srcRgn1, Type_UD); in lscAdd64AosEmu()
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| /dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/visa/ |
| H A D | HWConformity.cpp | 2194 …G4_DstRegRegion* accDstOpnd = builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, tmpType); in doGenerateMacl()
2419 …G4_DstRegRegion* acc_dst_opnd = builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, tmp_ty… in fixMULInst()
2463 builder.phyregpool.getAcc0Reg(), 0, 0, rd, tmp_type); in fixMULInst()
2768 builder.phyregpool.getAcc0Reg(), in fixMULHInst()
4891 builder.phyregpool.getAcc0Reg(), in fixSADA2Inst()
4908 builder.phyregpool.getAcc0Reg(), in fixSADA2Inst()
7256 builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, Type_NF) : in expandPlaneMacro()
7267 … builder.createSrc(builder.phyregpool.getAcc0Reg(), 0, 0, builder.getRegionStride1(), Type_NF) : in expandPlaneMacro()
9443 …G4_DstRegRegion* accDstOpnd = builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, tmpType); in fixMadwInst()
9468 auto accSrcOpndMov = builder.createSrc(builder.phyregpool.getAcc0Reg(), 0, 0, in fixMadwInst()
[all …]
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| H A D | Optimizer.cpp | 7155 G4_Areg* accReg = start >= 16 ? phyregpool.getAcc1Reg() : phyregpool.getAcc0Reg(); in createSubSrcOperand()
7234 … G4_Areg* accReg = start >= 16 ? phyregpool.getAcc1Reg() : phyregpool.getAcc0Reg(); in createSubDstOperand()
7759 builder.createDst(builder.phyregpool.getAcc0Reg(),0, 0, 1, Type_F), in HWWorkaround()
10655 …G4_DstRegRegion *accDstOpnd = builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, Adjusted… in processCandidates()
10678 mod, Direct, builder.phyregpool.getAcc0Reg(), 0, 0, rd, AdjustedType); in processCandidates()
10686 …G4_DstRegRegion *accDstOpnd = builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, Adjusted… in processCandidates()
10703 G4_SrcRegRegion *accSrcOpnd = builder.createSrc(builder.phyregpool.getAcc0Reg(), 0, 0, rd, in processCandidates()
13527 …G4_DstRegRegion* accDstOpnd = builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, tmpType); in expandMulPostSchedule()
13609 …G4_DstRegRegion* accDstOpnd = builder.createDst(builder.phyregpool.getAcc0Reg(), 0, 0, 1, tmpType); in expandMadwPostSchedule()
13642 auto accSrcOpndMov = builder.createSrc(builder.phyregpool.getAcc0Reg(), 0, 0, in expandMadwPostSchedule()
[all …]
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| H A D | BuildIRImpl.cpp | 1626 auto accSrc = createSrc(phyregpool.getAcc0Reg(), 0, 0, rd, accType); in createMach()
1628 auto accDSt = createDst(phyregpool.getAcc0Reg(), 0, 0, 1, accType); in createMach()
1644 auto accSrc = createSrc(phyregpool.getAcc0Reg(), 0, 0, rd, accType); in createMacl()
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| H A D | G4_IR.hpp | 3988 G4_Areg* getAcc0Reg() { return ARF_Table[AREG_ACC0]; } in getAcc0Reg() function in vISA::PhyRegPool
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| /dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/visa/Passes/ |
| H A D | AccSubstitution.cpp | 695 G4_Areg* accReg = useAcc1 ? builder.phyregpool.getAcc1Reg() : builder.phyregpool.getAcc0Reg(); in replaceDstWithAcc()
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