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/dports/cad/openroad/OpenROAD-2.0/src/ICeWall/test/coyote_tc/
H A D1_synth.sdc4 # set_dont_touch [get_ports *]
5 set_load -pin_load 3 [get_ports rocc_cmd_v_o]
6 set_load -pin_load 3 [get_ports {rocc_cmd_data_o_15}]
7 set_load -pin_load 3 [get_ports {rocc_cmd_data_o_14}]
8 set_load -pin_load 3 [get_ports {rocc_cmd_data_o_13}]
9 set_load -pin_load 3 [get_ports {rocc_cmd_data_o_12}]
10 set_load -pin_load 3 [get_ports {rocc_cmd_data_o_11}]
12 set_load -pin_load 3 [get_ports {rocc_cmd_data_o_9}]
22 set_load -pin_load 3 [get_ports rocc_resp_ready_o]
93 set_load -pin_load 3 [get_ports fsb_node_v_o]
[all …]
/dports/cad/openroad/OpenROAD-2.0/src/replace/test/design/a2a/wb_dma_top/
H A Dwb_dma_top.sdc6 set_driving_cell -lib_cell in01f80 [get_ports rst_i]
254 set_load -pin_load 1 [get_ports wb0_ack_o]
255 set_load -pin_load 1 [get_ports wb0_err_o]
256 set_load -pin_load 1 [get_ports wb0_rty_o]
325 set_load -pin_load 1 [get_ports wb0_we_o]
326 set_load -pin_load 1 [get_ports wb0_cyc_o]
327 set_load -pin_load 1 [get_ports wb0_stb_o]
360 set_load -pin_load 1 [get_ports wb1_ack_o]
431 set_load -pin_load 1 [get_ports wb1_we_o]
435 set_load -pin_load 1 [get_ports inta_o]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c5315/
H A Dc5315.sdc1 set_input_delay 0 -min -rise [get_ports n562]
2 set_input_delay 0 -min -fall [get_ports n562]
3 set_input_delay 0 -max -rise [get_ports n562]
4 set_input_delay 0 -max -fall [get_ports n562]
9 set_input_delay 0 -min -rise [get_ports n123]
10 set_input_delay 0 -min -fall [get_ports n123]
11 set_input_delay 0 -max -rise [get_ports n123]
12 set_input_delay 0 -max -fall [get_ports n123]
17 set_input_delay 0 -min -rise [get_ports n315]
18 set_input_delay 0 -min -fall [get_ports n315]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c7552/
H A Dc7552.sdc1 set_input_delay 0 -min -rise [get_ports n94]
2 set_input_delay 0 -min -fall [get_ports n94]
3 set_input_delay 0 -max -rise [get_ports n94]
4 set_input_delay 0 -max -fall [get_ports n94]
5 set_input_transition 5 -min -rise [get_ports n94]
9 set_input_delay 0 -min -rise [get_ports n18]
10 set_input_delay 0 -min -fall [get_ports n18]
11 set_input_delay 0 -max -rise [get_ports n18]
12 set_input_delay 0 -max -fall [get_ports n18]
1669 set_load -pin_load 4 [get_ports n2]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c7552_slack/
H A Dc7552_slack.sdc1 set_input_delay 0 -min -rise [get_ports n94]
2 set_input_delay 0 -min -fall [get_ports n94]
3 set_input_delay 0 -max -rise [get_ports n94]
4 set_input_delay 0 -max -fall [get_ports n94]
5 set_input_transition 5 -min -rise [get_ports n94]
9 set_input_delay 0 -min -rise [get_ports n18]
10 set_input_delay 0 -min -fall [get_ports n18]
11 set_input_delay 0 -max -rise [get_ports n18]
12 set_input_delay 0 -max -fall [get_ports n18]
1669 set_load -pin_load 4 [get_ports n2]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c2670/
H A Dc2670.sdc1 set_input_delay 0 -min -rise [get_ports n2678]
2 set_input_delay 0 -min -fall [get_ports n2678]
3 set_input_delay 0 -max -rise [get_ports n2678]
4 set_input_delay 0 -max -fall [get_ports n2678]
9 set_input_delay 0 -min -rise [get_ports n8]
10 set_input_delay 0 -min -fall [get_ports n8]
11 set_input_delay 0 -max -rise [get_ports n8]
12 set_input_delay 0 -max -fall [get_ports n8]
25 set_input_delay 0 -min -rise [get_ports n2]
26 set_input_delay 0 -min -fall [get_ports n2]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c880/
H A Dc880.sdc1 set_input_delay 0 -min -rise [get_ports n201gat]
2 set_input_delay 0 -min -fall [get_ports n201gat]
3 set_input_delay 0 -max -rise [get_ports n201gat]
4 set_input_delay 0 -max -fall [get_ports n201gat]
9 set_input_delay 0 -min -rise [get_ports n189gat]
10 set_input_delay 0 -min -fall [get_ports n189gat]
11 set_input_delay 0 -max -rise [get_ports n189gat]
12 set_input_delay 0 -max -fall [get_ports n189gat]
17 set_input_delay 0 -min -rise [get_ports n17gat]
18 set_input_delay 0 -min -fall [get_ports n17gat]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c3540/
H A Dc3540.sdc1 set_input_delay 0 -min -rise [get_ports n317]
2 set_input_delay 0 -min -fall [get_ports n317]
3 set_input_delay 0 -max -rise [get_ports n317]
4 set_input_delay 0 -max -fall [get_ports n317]
9 set_input_delay 0 -min -rise [get_ports n179]
10 set_input_delay 0 -min -fall [get_ports n179]
11 set_input_delay 0 -max -rise [get_ports n179]
12 set_input_delay 0 -max -fall [get_ports n179]
406 set_load -pin_load 4 [get_ports n399]
411 set_load -pin_load 4 [get_ports n361]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c6288/
H A Dc6288.sdc1 set_input_delay 0 -min -rise [get_ports n341gat]
2 set_input_delay 0 -min -fall [get_ports n341gat]
3 set_input_delay 0 -max -rise [get_ports n341gat]
4 set_input_delay 0 -max -fall [get_ports n341gat]
9 set_input_delay 0 -min -rise [get_ports n409gat]
10 set_input_delay 0 -min -fall [get_ports n409gat]
11 set_input_delay 0 -max -rise [get_ports n409gat]
12 set_input_delay 0 -max -fall [get_ports n409gat]
262 set_load -pin_load 4 [get_ports n6260gat]
267 set_load -pin_load 4 [get_ports n6270gat]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c432/
H A Dc432.sdc1 set_input_delay 0 -min -rise [get_ports n43gat]
2 set_input_delay 0 -min -fall [get_ports n43gat]
3 set_input_delay 0 -max -rise [get_ports n43gat]
4 set_input_delay 0 -max -fall [get_ports n43gat]
9 set_input_delay 0 -min -rise [get_ports n17gat]
10 set_input_delay 0 -min -fall [get_ports n17gat]
11 set_input_delay 0 -max -rise [get_ports n17gat]
12 set_input_delay 0 -max -fall [get_ports n17gat]
294 set_load -pin_load 4 [get_ports n432gat]
299 set_load -pin_load 4 [get_ports n430gat]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c1355/
H A Dc1355.sdc1 set_input_delay 0 -min -rise [get_ports n43gat]
2 set_input_delay 0 -min -fall [get_ports n43gat]
3 set_input_delay 0 -max -rise [get_ports n43gat]
4 set_input_delay 0 -max -fall [get_ports n43gat]
9 set_input_delay 0 -min -rise [get_ports n190gat]
10 set_input_delay 0 -min -fall [get_ports n190gat]
11 set_input_delay 0 -max -rise [get_ports n190gat]
12 set_input_delay 0 -max -fall [get_ports n190gat]
17 set_input_delay 0 -min -rise [get_ports n99gat]
18 set_input_delay 0 -min -fall [get_ports n99gat]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c499/
H A Dc499.sdc1 set_input_delay 0 -min -rise [get_ports nid20]
2 set_input_delay 0 -min -fall [get_ports nid20]
3 set_input_delay 0 -max -rise [get_ports nid20]
4 set_input_delay 0 -max -fall [get_ports nid20]
9 set_input_delay 0 -min -rise [get_ports nid6]
10 set_input_delay 0 -min -fall [get_ports nid6]
11 set_input_delay 0 -max -rise [get_ports nid6]
12 set_input_delay 0 -max -fall [get_ports nid6]
339 set_load -pin_load 4 [get_ports nod6]
379 set_load -pin_load 4 [get_ports nod5]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/c1908/
H A Dc1908.sdc1 set_input_delay 0 -min -rise [get_ports n227]
2 set_input_delay 0 -min -fall [get_ports n227]
3 set_input_delay 0 -max -rise [get_ports n227]
4 set_input_delay 0 -max -fall [get_ports n227]
270 set_load -pin_load 4 [get_ports n66]
275 set_load -pin_load 4 [get_ports n72]
280 set_load -pin_load 4 [get_ports n69]
285 set_load -pin_load 4 [get_ports n54]
340 set_load -pin_load 4 [get_ports n9]
360 set_load -pin_load 4 [get_ports n6]
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dmb_pins.xdc13 set_property PACKAGE_PIN AK15 [get_ports {ENA_PAPWR}]
14 set_property IOSTANDARD LVCMOS33 [get_ports {ENA_PAPWR}]
32 set_property PACKAGE_PIN V5 [get_ports {SFP1_RX_N}]
33 set_property PACKAGE_PIN V6 [get_ports {SFP1_RX_P}]
34 set_property PACKAGE_PIN T1 [get_ports {SFP1_TX_N}]
35 set_property PACKAGE_PIN T2 [get_ports {SFP1_TX_P}]
50 set_property PACKAGE_PIN AJ18 [get_ports {SFP1_RS0}]
51 set_property PACKAGE_PIN AK16 [get_ports {SFP1_RS1}]
52 set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_RS*}]
57 set_property PACKAGE_PIN AB16 [get_ports {LED_ACT1}]
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300.xdc14 set_property PACKAGE_PIN AA3 [get_ports SFP0_RX_n]
15 set_property PACKAGE_PIN AA4 [get_ports SFP0_RX_p]
18 set_property PACKAGE_PIN Y1 [get_ports SFP0_TX_n]
19 set_property PACKAGE_PIN Y2 [get_ports SFP0_TX_p]
22 set_property PACKAGE_PIN T5 [get_ports SFP1_RX_n]
23 set_property PACKAGE_PIN T6 [get_ports SFP1_RX_p]
26 set_property PACKAGE_PIN P1 [get_ports SFP1_TX_n]
27 set_property PACKAGE_PIN P2 [get_ports SFP1_TX_p]
385 set_property PACKAGE_PIN AD18 [get_ports IoRxClock]
474 set_property IOSTANDARD LVTTL [get_ports aIrq]
[all …]
/dports/cad/openroad/OpenROAD-2.0/src/replace/test/design/nangate45/dynamic_node_top_wrap/
H A Ddynamic_node_top_wrap.sdc9 create_clock [get_ports clk] -period 6 -waveform {0 3}
10 set_input_delay -clock clk -max 5.1 [get_ports clk]
11 set_input_delay -clock clk -min 4.02 [get_ports clk]
12 set_input_delay -clock clk -max 5.1 [get_ports reset_in]
13 set_input_delay -clock clk -min 4.02 [get_ports reset_in]
14 set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[63]}]
15 set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[63]}]
16 set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[62]}]
17 set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[62]}]
18 set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[61]}]
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_idle_pins.xdc7 set_property PACKAGE_PIN H19 [get_ports {DB_IO[0]}]
8 set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[0]}]
14 set_property PACKAGE_PIN F19 [get_ports {DB_IO[1]}]
21 set_property PACKAGE_PIN G19 [get_ports {DB_IO[2]}]
25 set_property PACKAGE_PIN E19 [get_ports {DB_IO[3]}]
29 set_property PACKAGE_PIN E20 [get_ports {DB_IO[4]}]
33 set_property PACKAGE_PIN G21 [get_ports {DB_IO[5]}]
65 #set_property PACKAGE_PIN J21 [get_ports {}]
66 #set_property IOSTANDARD LVCMOS18 [get_ports {}]
73 #set_property PACKAGE_PIN J22 [get_ports {}]
[all …]
H A De31x_pins.xdc7 set_property PACKAGE_PIN H19 [get_ports {TX_BANDSEL[2]}]
29 set_property PACKAGE_PIN E20 [get_ports VCTXRX2_V2]
37 set_property PACKAGE_PIN G22 [get_ports TX_ENABLE1A]
65 #set_property PACKAGE_PIN J21 [get_ports DB_SCL]
73 #set_property PACKAGE_PIN J22 [get_ports DB_SDA]
109 set_property PACKAGE_PIN E18 [get_ports VCRX1_V1]
117 set_property PACKAGE_PIN F18 [get_ports VCRX1_V2]
121 set_property PACKAGE_PIN M20 [get_ports TCXO_CLK]
126 set_property PACKAGE_PIN F17 [get_ports VCRX2_V1]
201 set_property PACKAGE_PIN W6 [get_ports CAT_CS]
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dmb_pins.xdc13 set_property PACKAGE_PIN AF25 [get_ports {FPGA_GPIO[0]}]
14 set_property PACKAGE_PIN AE25 [get_ports {FPGA_GPIO[1]}]
15 set_property PACKAGE_PIN AG26 [get_ports {FPGA_GPIO[2]}]
16 set_property PACKAGE_PIN AG27 [get_ports {FPGA_GPIO[3]}]
17 set_property PACKAGE_PIN AE26 [get_ports {FPGA_GPIO[4]}]
18 set_property PACKAGE_PIN AB26 [get_ports {FPGA_GPIO[5]}]
19 set_property PACKAGE_PIN AF27 [get_ports {FPGA_GPIO[6]}]
20 set_property PACKAGE_PIN AA27 [get_ports {FPGA_GPIO[7]}]
66 set_property PACKAGE_PIN AA18 [get_ports WB_20MHZ_P]
93 set_property PACKAGE_PIN W30 [get_ports GPS_1PPS]
[all …]
/dports/cad/openroad/OpenROAD-2.0/src/replace/test/design/nangate45/aes_cipher_top/
H A Daes_cipher_top.sdc9 create_clock [get_ports clk] -period 5 -waveform {0 2.5}
11 set_input_delay -clock clk -max 0 [get_ports clk]
12 set_input_delay -clock clk -max 0 [get_ports rst]
13 set_input_delay -clock clk -max 0 [get_ports ld]
14 set_input_delay -clock clk -max 0 [get_ports {key[127]}]
15 set_input_delay -clock clk -max 0 [get_ports {key[126]}]
16 set_input_delay -clock clk -max 0 [get_ports {key[125]}]
17 set_input_delay -clock clk -max 0 [get_ports {key[124]}]
18 set_input_delay -clock clk -max 0 [get_ports {key[123]}]
270 set_input_delay -clock clk -max 0 [get_ports SE]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/des_perf/
H A Ddes_perf.sdc1 create_clock -period 100 -name x677 [get_ports x677]
1886 set_load -pin_load 4 [get_ports x54]
1891 set_load -pin_load 4 [get_ports x562]
1896 set_load -pin_load 4 [get_ports x625]
1901 set_load -pin_load 4 [get_ports x428]
1911 set_load -pin_load 4 [get_ports x13]
2076 set_load -pin_load 4 [get_ports x93]
2121 set_load -pin_load 4 [get_ports x82]
2141 set_load -pin_load 4 [get_ports x0]
2176 set_load -pin_load 4 [get_ports x74]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/vga_lcd/
H A Dvga_lcd.sdc1 create_clock -period 100 -name x2469 [get_ports x2469]
753 set_load -pin_load 4 [get_ports x40]
783 set_load -pin_load 4 [get_ports x86]
888 set_load -pin_load 4 [get_ports x24]
948 set_load -pin_load 4 [get_ports x73]
958 set_load -pin_load 4 [get_ports x79]
1053 set_load -pin_load 4 [get_ports x93]
1078 set_load -pin_load 4 [get_ports x32]
1103 set_load -pin_load 4 [get_ports x99]
1123 set_load -pin_load 4 [get_ports x0]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/aes_core/
H A Daes_core.sdc1 create_clock -period 100 -name x7698 [get_ports x7698]
2086 set_load -pin_load 4 [get_ports x643]
2091 set_load -pin_load 4 [get_ports x492]
2176 set_load -pin_load 4 [get_ports x55]
2201 set_load -pin_load 4 [get_ports x8]
2221 set_load -pin_load 4 [get_ports x71]
2241 set_load -pin_load 4 [get_ports x90]
2326 set_load -pin_load 4 [get_ports x23]
2366 set_load -pin_load 4 [get_ports x0]
2526 set_load -pin_load 4 [get_ports x33]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/ac97_ctrl/
H A Dac97_ctrl.sdc1 create_clock -period 100 -name x821 [get_ports x821]
678 set_load -pin_load 4 [get_ports x718]
683 set_load -pin_load 4 [get_ports x124]
688 set_load -pin_load 4 [get_ports x30]
703 set_load -pin_load 4 [get_ports x84]
783 set_load -pin_load 4 [get_ports x63]
798 set_load -pin_load 4 [get_ports x96]
818 set_load -pin_load 4 [get_ports x0]
873 set_load -pin_load 4 [get_ports x77]
893 set_load -pin_load 4 [get_ports x14]
[all …]
/dports/cad/opentimer/OpenTimer-18d28ff/benchmark/s1494/
H A Ds1494.sdc86 set_load -pin_load 4 [get_ports v13_D_7]
91 set_load -pin_load 4 [get_ports v13_D_15]
96 set_load -pin_load 4 [get_ports v13_D_11]
101 set_load -pin_load 4 [get_ports v13_D_23]
106 set_load -pin_load 4 [get_ports v13_D_17]
111 set_load -pin_load 4 [get_ports v13_D_9]
116 set_load -pin_load 4 [get_ports v13_D_22]
121 set_load -pin_load 4 [get_ports v13_D_20]
126 set_load -pin_load 4 [get_ports v13_D_19]
141 set_load -pin_load 4 [get_ports v13_D_8]
[all …]

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