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Searched refs:gmii_rx_dv (Results 1 – 12 of 12) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/
H A Ddemo_one_gig_pcs_pma_mdio.v203 wire gmii_rx_dv; net
306 .gmii_rx_dv (gmii_rx_dv),
337 .gmii_rx_dv (gmii_rx_dv),
H A Done_gig_eth_loopback_tb.sv141 .gmii_rx_dv(m_gmii_rx_dv), // Received control signal to client MAC.
204 .gmii_rx_dv(s_gmii_rx_dv), // Received control signal to client MAC.
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/
H A Done_gige_phy.v25 output reg gmii_rx_dv, // Received control signal to client MAC. port
56 gmii_rx_dv <= gmii_rx_dv_int;
82 .gmii_rx_dv (gmii_rx_dv_int),
H A Done_gige_phy.xdc84 #set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv]
127 set_property SLEW FAST [get_ports gmii_rx_dv]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/
H A Done_gige_phy.v25 output reg gmii_rx_dv, // Received control signal to client MAC. port
57 gmii_rx_dv <= gmii_rx_dv_int;
83 .gmii_rx_dv (gmii_rx_dv_int),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/
H A Done_gige_phy.v27 output reg gmii_rx_dv, // Received control signal to client MAC. port
60 gmii_rx_dv <= gmii_rx_dv_int;
86 .gmii_rx_dv (gmii_rx_dv_int),
H A Done_gig_eth_pcs_pma_support.v90 output gmii_rx_dv, // Received control signal to client MAC. port
171 .gmii_rx_dv (gmii_rx_dv),
H A Done_gige_phy.xdc84 #set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv]
127 set_property SLEW FAST [get_ports gmii_rx_dv]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_mgt_io_core.v423 wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; net
451 .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC.
482 .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC.
511 .GMII_RX_DV(gmii_rx_dv),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_sfpp_io_core.v202 wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; net
224 .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC.
248 .GMII_RX_DV(gmii_rx_dv),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dn3xx_mgt_io_core.v370 wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; net
395 .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC.
420 .GMII_RX_DV(gmii_rx_dv),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/simple_gemac/
H A Dgmii_to_axis.v25 input gmii_rx_dv, port
80 .GMII_RX_DV(gmii_rx_dv),