Searched refs:gpio_mmio_base (Results 1 – 11 of 11) sorted by relevance
121 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_i2c_reset()122 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); in intel_i2c_reset()268 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_hw_status()341 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_idle()380 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_read()412 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_write()462 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_index_read()507 reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer()629 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; in intel_setup_gmbus()631 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; in intel_setup_gmbus()[all …]
1528 uint32_t gpio_mmio_base; member
852 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; in intel_gmbus_setup()858 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; in intel_gmbus_setup()
3359 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \3377 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */3386 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */3401 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */3409 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */3410 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */3416 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
832 u32 gpio_mmio_base; member