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Searched refs:gpt_tctl (Results 1 – 25 of 140) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c94 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
100 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
103 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
104 &regs->gpt_tctl); in timer_init()
105 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c94 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
100 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
103 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
104 &regs->gpt_tctl); in timer_init()
105 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c94 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
100 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
103 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
104 &regs->gpt_tctl); in timer_init()
105 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c94 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
100 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
103 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
104 &regs->gpt_tctl); in timer_init()
105 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/cpu/arm926ejs/mx27/
H A Dtimer.c99 writel(GPTCR_SWR, &regs->gpt_tctl); in timer_init()
105 writel(0, &regs->gpt_tctl); /* We have no udelay by now */ in timer_init()
108 writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
109 &regs->gpt_tctl); in timer_init()
110 writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl); in timer_init()

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