/dports/emulators/qemu42/qemu-4.2.1/hw/intc/ |
H A D | arm_gic.c | 148 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 288 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 293 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 294 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 304 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 310 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 316 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 322 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 816 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1855 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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H A D | arm_gic_common.c | 82 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), 324 s->h_hcr[i] = 0; in arm_gic_common_reset()
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/dports/emulators/qemu/qemu-6.2.0/hw/intc/ |
H A D | arm_gic.c | 151 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 291 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 296 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 297 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 307 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 313 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 319 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 325 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 838 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1877 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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H A D | arm_gic_common.c | 82 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), 324 s->h_hcr[i] = 0; in arm_gic_common_reset()
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/dports/emulators/qemu60/qemu-6.0.0/hw/intc/ |
H A D | arm_gic.c | 151 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 291 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 296 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 297 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 307 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 313 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 319 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 325 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 838 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1877 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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H A D | arm_gic_common.c | 82 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), 324 s->h_hcr[i] = 0; in arm_gic_common_reset()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/ |
H A D | arm_gic.c | 146 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 286 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 291 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 292 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 302 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 308 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 314 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 320 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 814 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1853 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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H A D | arm_gic_common.c | 79 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), 321 s->h_hcr[i] = 0; in arm_gic_common_reset()
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/dports/emulators/qemu5/qemu-5.2.0/hw/intc/ |
H A D | arm_gic.c | 148 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 288 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 293 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 294 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 304 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 310 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 316 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 322 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 835 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1874 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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H A D | arm_gic_common.c | 82 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), 324 s->h_hcr[i] = 0; in arm_gic_common_reset()
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/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/ |
H A D | arm_gic.c | 148 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 288 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 293 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 294 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 304 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 310 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 316 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 322 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 816 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1855 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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H A D | arm_gic_common.c | 82 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), 324 s->h_hcr[i] = 0; in arm_gic_common_reset()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/ |
H A D | arm_gic.c | 148 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { 288 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { 293 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && 294 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { 304 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && 310 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && 316 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && 322 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && 835 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; 1874 *data = s->h_hcr[cpu]; [all …]
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H A D | arm_gic_common.c | 82 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), 324 s->h_hcr[i] = 0; in arm_gic_common_reset()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/ |
H A D | arm_gic.c | 148 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 288 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 293 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 294 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 304 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 310 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 316 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 322 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 835 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1874 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/ |
H A D | arm_gic.c | 151 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { in gic_irq_signaling_enabled() 291 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { in gic_compute_misr() 296 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && in gic_compute_misr() 297 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { in gic_compute_misr() 307 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && in gic_compute_misr() 313 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && in gic_compute_misr() 319 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && in gic_compute_misr() 325 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && in gic_compute_misr() 838 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; in gic_deactivate_irq() 1877 *data = s->h_hcr[cpu]; in gic_hyp_read() [all …]
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/dports/emulators/qemu42/qemu-4.2.1/include/hw/intc/ |
H A D | arm_gic_common.h | 119 uint32_t h_hcr[GIC_NCPU]; member
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/dports/emulators/qemu/qemu-6.2.0/include/hw/intc/ |
H A D | arm_gic_common.h | 121 uint32_t h_hcr[GIC_NCPU]; member
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/dports/emulators/qemu60/qemu-6.0.0/include/hw/intc/ |
H A D | arm_gic_common.h | 121 uint32_t h_hcr[GIC_NCPU]; member
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/intc/ |
H A D | arm_gic_common.h | 119 uint32_t h_hcr[GIC_NCPU]; member
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/dports/emulators/qemu5/qemu-5.2.0/include/hw/intc/ |
H A D | arm_gic_common.h | 121 uint32_t h_hcr[GIC_NCPU]; member
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/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/intc/ |
H A D | arm_gic_common.h | 119 uint32_t h_hcr[GIC_NCPU]; member
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/intc/ |
H A D | arm_gic_common.h | 120 uint32_t h_hcr[GIC_NCPU];
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/intc/ |
H A D | arm_gic_common.h | 121 uint32_t h_hcr[GIC_NCPU]; member
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/intc/ |
H A D | arm_gic_common.h | 120 uint32_t h_hcr[GIC_NCPU]; member
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