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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
[all …]
/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/riscv/lib/
H A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
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