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Searched refs:hasStdExtZfh (Results 1 – 25 of 29) sorted by relevance

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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h125 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVTargetTransformInfo.h90 return ST->hasStdExtZfh(); in isLegalElementTypeForRVV()
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
H A DRISCVISelLowering.cpp86 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
132 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
311 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
314 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
641 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
999 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
1011 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
1241 if (!Subtarget.hasStdExtZfh()) in useRVVForFixedLengthVectorVT()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
8492 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/
H A DRISCVSubtarget.h125 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVTargetTransformInfo.h90 return ST->hasStdExtZfh(); in isLegalElementTypeForRVV()
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
H A DRISCVISelLowering.cpp86 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
132 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
311 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
314 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
641 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
999 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
1011 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
1241 if (!Subtarget.hasStdExtZfh()) in useRVVForFixedLengthVectorVT()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
8492 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h124 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVISelLowering.cpp86 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
128 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
283 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
286 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
444 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
603 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
615 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
690 Subtarget.hasStdExtZfh()) && in LowerOperation()
694 if (Op.getValueType() == MVT::f16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
4149 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
[all …]
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h125 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVTargetTransformInfo.h90 return ST->hasStdExtZfh(); in isLegalElementTypeForRVV()
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h121 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h125 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVTargetTransformInfo.h90 return ST->hasStdExtZfh(); in isLegalElementTypeForRVV()
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h124 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVISelLowering.cpp86 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
128 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
283 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
286 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
444 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
603 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
615 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
690 Subtarget.hasStdExtZfh()) && in LowerOperation()
694 if (Op.getValueType() == MVT::f16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
4149 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
[all …]
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h125 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVTargetTransformInfo.h90 return ST->hasStdExtZfh(); in isLegalElementTypeForRVV()
H A DRISCV.td48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,

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