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Searched refs:hold_dly (Results 1 – 6 of 6) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/spi/
H A Dspi-mt65xx.c515 u16 setup_dly, hold_dly, inactive_dly; in mtk_spi_set_hw_cs_timing() local
527 hold_dly = hold ? hold->value : 1; in mtk_spi_set_hw_cs_timing()
533 reg_val |= (((hold_dly - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
540 reg_val |= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
H A Dspi-tegra114.c726 u8 setup_dly, hold_dly, inactive_dly; in tegra_spi_set_hw_cs_timing() local
742 hold_dly = hold ? hold->value : 0; in tegra_spi_set_hw_cs_timing()
746 hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES); in tegra_spi_set_hw_cs_timing()
747 if (setup_dly && hold_dly) { in tegra_spi_set_hw_cs_timing()
748 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); in tegra_spi_set_hw_cs_timing()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/spi/
H A Dspi-mt65xx.c515 u16 setup_dly, hold_dly, inactive_dly; in mtk_spi_set_hw_cs_timing() local
527 hold_dly = hold ? hold->value : 1; in mtk_spi_set_hw_cs_timing()
533 reg_val |= (((hold_dly - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
540 reg_val |= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
H A Dspi-tegra114.c726 u8 setup_dly, hold_dly, inactive_dly; in tegra_spi_set_hw_cs_timing() local
742 hold_dly = hold ? hold->value : 0; in tegra_spi_set_hw_cs_timing()
746 hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES); in tegra_spi_set_hw_cs_timing()
747 if (setup_dly && hold_dly) { in tegra_spi_set_hw_cs_timing()
748 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); in tegra_spi_set_hw_cs_timing()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/spi/
H A Dspi-mt65xx.c515 u16 setup_dly, hold_dly, inactive_dly; in mtk_spi_set_hw_cs_timing() local
527 hold_dly = hold ? hold->value : 1; in mtk_spi_set_hw_cs_timing()
533 reg_val |= (((hold_dly - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
540 reg_val |= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
H A Dspi-tegra114.c726 u8 setup_dly, hold_dly, inactive_dly; in tegra_spi_set_hw_cs_timing() local
742 hold_dly = hold ? hold->value : 0; in tegra_spi_set_hw_cs_timing()
746 hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES); in tegra_spi_set_hw_cs_timing()
747 if (setup_dly && hold_dly) { in tegra_spi_set_hw_cs_timing()
748 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); in tegra_spi_set_hw_cs_timing()