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/dports/devel/avr-gdb/gdb-7.3.1/sim/bfin/
H A Ddv-bfin_sic.c575 { "pll", ENC(0, 0), 0, input_port, },
576 { "dma_stat", ENC(0, 1), 0, input_port, },
577 { "ppi@0", ENC(0, 2), 0, input_port, },
578 { "sport@0_stat", ENC(0, 3), 0, input_port, },
579 { "sport@1_stat", ENC(0, 4), 0, input_port, },
580 { "uart2@0_stat", ENC(0, 5), 0, input_port, },
581 { "uart2@1_stat", ENC(0, 6), 0, input_port, },
582 { "spi@0", ENC(0, 7), 0, input_port, },
583 { "spi@1", ENC(0, 8), 0, input_port, },
584 { "can_stat", ENC(0, 9), 0, input_port, },
[all …]
H A Ddv-bfin_dmac.c96 { "ppi@0", 0, 0, input_port, },
97 { "rsi", 1, 0, input_port, },
98 { "sport@0_rx", 2, 0, input_port, },
99 { "sport@0_tx", 3, 0, input_port, },
100 { "sport@1_tx", 4, 0, input_port, },
101 { "sport@1_rx", 5, 0, input_port, },
102 { "spi@0", 6, 0, input_port, },
103 { "spi@1", 7, 0, input_port, },
104 { "uart2@0_rx", 8, 0, input_port, },
105 { "uart2@0_tx", 9, 0, input_port, },
[all …]
/dports/devel/gdb761/gdb-7.6.1/sim/bfin/
H A Ddv-bfin_dmac.c96 { "ppi@0", 0, 0, input_port, },
97 { "rsi", 1, 0, input_port, },
98 { "sport@0_rx", 2, 0, input_port, },
99 { "sport@0_tx", 3, 0, input_port, },
100 { "sport@1_tx", 4, 0, input_port, },
101 { "sport@1_rx", 5, 0, input_port, },
102 { "spi@0", 6, 0, input_port, },
103 { "spi@1", 7, 0, input_port, },
104 { "uart2@0_rx", 8, 0, input_port, },
105 { "uart2@0_tx", 9, 0, input_port, },
[all …]
H A Ddv-bfin_pint.c176 { "piq0@"#n, ENC(n, 0), 0, input_port, }, \
177 { "piq1@"#n, ENC(n, 1), 0, input_port, }, \
178 { "piq2@"#n, ENC(n, 2), 0, input_port, }, \
179 { "piq3@"#n, ENC(n, 3), 0, input_port, }, \
180 { "piq4@"#n, ENC(n, 4), 0, input_port, }, \
181 { "piq5@"#n, ENC(n, 5), 0, input_port, }, \
182 { "piq6@"#n, ENC(n, 6), 0, input_port, }, \
183 { "piq7@"#n, ENC(n, 7), 0, input_port, }, \
184 { "piq8@"#n, ENC(n, 8), 0, input_port, }, \
185 { "piq9@"#n, ENC(n, 9), 0, input_port, }, \
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/sim/lm32/
H A Ddv-lm32cpu.c70 {"int0", INT0_PORT, 0, input_port,},
71 {"int1", INT1_PORT, 0, input_port,},
72 {"int2", INT2_PORT, 0, input_port,},
73 {"int3", INT3_PORT, 0, input_port,},
74 {"int4", INT4_PORT, 0, input_port,},
75 {"int5", INT5_PORT, 0, input_port,},
76 {"int6", INT6_PORT, 0, input_port,},
77 {"int7", INT7_PORT, 0, input_port,},
78 {"int8", INT8_PORT, 0, input_port,},
79 {"int9", INT9_PORT, 0, input_port,},
[all …]
/dports/devel/gdb761/gdb-7.6.1/sim/lm32/
H A Ddv-lm32cpu.c70 {"int0", INT0_PORT, 0, input_port,},
71 {"int1", INT1_PORT, 0, input_port,},
72 {"int2", INT2_PORT, 0, input_port,},
73 {"int3", INT3_PORT, 0, input_port,},
74 {"int4", INT4_PORT, 0, input_port,},
75 {"int5", INT5_PORT, 0, input_port,},
76 {"int6", INT6_PORT, 0, input_port,},
77 {"int7", INT7_PORT, 0, input_port,},
78 {"int8", INT8_PORT, 0, input_port,},
79 {"int9", INT9_PORT, 0, input_port,},
[all …]
/dports/devel/tbb/oneTBB-2020.3/examples/graph/logic_sim/
H A Dfour_bit_adder.h44 make_edge(output_port<1>(four_adders[0]), input_port<0>(four_adders[1])); in make_connections()
45 make_edge(output_port<1>(four_adders[1]), input_port<0>(four_adders[2])); in make_connections()
46 make_edge(output_port<1>(four_adders[2]), input_port<0>(four_adders[3])); in make_connections()
50 …input_port<0>(four_adders[0]/*CI*/), input_port<1>(four_adders[0]), input_port<2>(four_adders[0]),… in set_up_composite()
H A Dtest_all.cpp74 make_edge(input.get_out(), input_port<0>(b)); in main()
93 make_edge(input.get_out(), input_port<0>(n)); in main()
113 make_edge(input0.get_out(), input_port<0>(a)); in main()
114 make_edge(input1.get_out(), input_port<1>(a)); in main()
143 make_edge(input0.get_out(), input_port<0>(o)); in main()
144 make_edge(input1.get_out(), input_port<1>(o)); in main()
145 make_edge(input2.get_out(), input_port<2>(o)); in main()
189 make_edge(input0.get_out(), input_port<0>(x)); in main()
190 make_edge(input1.get_out(), input_port<1>(x)); in main()
219 make_edge(input0.get_out(), input_port<0>(n)); in main()
[all …]
H A DD_latch.h37 make_edge(D_port, input_port<0>(a_not)); in D_latch()
38 make_edge(D_port, input_port<1>(second_and)); in D_latch()
39 make_edge(E_port, input_port<1>(first_and)); in D_latch()
40 make_edge(E_port, input_port<0>(second_and)); in D_latch()
41 make_edge(a_not, input_port<0>(first_and)); in D_latch()
42 make_edge(first_and, input_port<0>(first_nor)); in D_latch()
43 make_edge(second_and, input_port<1>(second_nor)); in D_latch()
44 make_edge(first_nor, input_port<0>(second_nor)); in D_latch()
45 make_edge(second_nor, input_port<1>(first_nor)); in D_latch()
/dports/devel/taskflow/taskflow-3.2.0/3rd-party/tbb/examples/graph/logic_sim/
H A Dfour_bit_adder.h44 make_edge(output_port<1>(four_adders[0]), input_port<0>(four_adders[1])); in make_connections()
45 make_edge(output_port<1>(four_adders[1]), input_port<0>(four_adders[2])); in make_connections()
46 make_edge(output_port<1>(four_adders[2]), input_port<0>(four_adders[3])); in make_connections()
50 …input_port<0>(four_adders[0]/*CI*/), input_port<1>(four_adders[0]), input_port<2>(four_adders[0]),… in set_up_composite()
H A Dtest_all.cpp74 make_edge(input.get_out(), input_port<0>(b)); in main()
93 make_edge(input.get_out(), input_port<0>(n)); in main()
113 make_edge(input0.get_out(), input_port<0>(a)); in main()
114 make_edge(input1.get_out(), input_port<1>(a)); in main()
143 make_edge(input0.get_out(), input_port<0>(o)); in main()
144 make_edge(input1.get_out(), input_port<1>(o)); in main()
145 make_edge(input2.get_out(), input_port<2>(o)); in main()
189 make_edge(input0.get_out(), input_port<0>(x)); in main()
190 make_edge(input1.get_out(), input_port<1>(x)); in main()
219 make_edge(input0.get_out(), input_port<0>(n)); in main()
[all …]
H A DD_latch.h37 make_edge(D_port, input_port<0>(a_not)); in D_latch()
38 make_edge(D_port, input_port<1>(second_and)); in D_latch()
39 make_edge(E_port, input_port<1>(first_and)); in D_latch()
40 make_edge(E_port, input_port<0>(second_and)); in D_latch()
41 make_edge(a_not, input_port<0>(first_and)); in D_latch()
42 make_edge(first_and, input_port<0>(first_nor)); in D_latch()
43 make_edge(second_and, input_port<1>(second_nor)); in D_latch()
44 make_edge(first_nor, input_port<0>(second_nor)); in D_latch()
45 make_edge(second_nor, input_port<1>(first_nor)); in D_latch()
/dports/devel/onetbb/oneTBB-2021.4.0/examples/graph/logic_sim/
H A Dfour_bit_adder.hpp58 make_edge(output_port<1>(four_adders[0]), input_port<0>(four_adders[1])); in make_connections()
59 make_edge(output_port<1>(four_adders[1]), input_port<0>(four_adders[2])); in make_connections()
60 make_edge(output_port<1>(four_adders[2]), input_port<0>(four_adders[3])); in make_connections()
64 input_port<1>(four_adders[0]), in set_up_composite()
65 input_port<2>(four_adders[0]), in set_up_composite()
66 input_port<1>(four_adders[1]), in set_up_composite()
67 input_port<2>(four_adders[1]), in set_up_composite()
68 input_port<1>(four_adders[2]), in set_up_composite()
69 input_port<2>(four_adders[2]), in set_up_composite()
70 input_port<1>(four_adders[3]), in set_up_composite()
[all …]
H A Dtest_all.cpp74 make_edge(input.get_out(), input_port<0>(b)); in main()
96 make_edge(input.get_out(), input_port<0>(n)); in main()
119 make_edge(input0.get_out(), input_port<0>(a)); in main()
120 make_edge(input1.get_out(), input_port<1>(a)); in main()
156 make_edge(input0.get_out(), input_port<0>(o)); in main()
157 make_edge(input1.get_out(), input_port<1>(o)); in main()
158 make_edge(input2.get_out(), input_port<2>(o)); in main()
219 make_edge(input0.get_out(), input_port<0>(x)); in main()
220 make_edge(input1.get_out(), input_port<1>(x)); in main()
255 make_edge(input0.get_out(), input_port<0>(n)); in main()
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Ddv-mn103int.c223 { "ack", ACK_PORT, 0, input_port, },
227 { "nmirq", G0_PORT + 0, 0, input_port, },
256 { "irq-0", G23_PORT, 0, input_port, },
257 { "irq-1", G24_PORT, 0, input_port, },
258 { "irq-2", G25_PORT, 0, input_port, },
259 { "irq-3", G26_PORT, 0, input_port, },
260 { "irq-4", G27_PORT, 0, input_port, },
261 { "irq-5", G28_PORT, 0, input_port, },
262 { "irq-6", G29_PORT, 0, input_port, },
263 { "irq-7", G30_PORT, 0, input_port, },
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/sim/mn10300/
H A Ddv-mn103int.c223 { "ack", ACK_PORT, 0, input_port, },
227 { "nmirq", G0_PORT + 0, 0, input_port, },
256 { "irq-0", G23_PORT, 0, input_port, },
257 { "irq-1", G24_PORT, 0, input_port, },
258 { "irq-2", G25_PORT, 0, input_port, },
259 { "irq-3", G26_PORT, 0, input_port, },
260 { "irq-4", G27_PORT, 0, input_port, },
261 { "irq-5", G28_PORT, 0, input_port, },
262 { "irq-6", G29_PORT, 0, input_port, },
263 { "irq-7", G30_PORT, 0, input_port, },
[all …]
/dports/devel/gdb761/gdb-7.6.1/sim/mn10300/
H A Ddv-mn103int.c222 { "ack", ACK_PORT, 0, input_port, },
226 { "nmirq", G0_PORT + 0, 0, input_port, },
255 { "irq-0", G23_PORT, 0, input_port, },
256 { "irq-1", G24_PORT, 0, input_port, },
257 { "irq-2", G25_PORT, 0, input_port, },
258 { "irq-3", G26_PORT, 0, input_port, },
259 { "irq-4", G27_PORT, 0, input_port, },
260 { "irq-5", G28_PORT, 0, input_port, },
261 { "irq-6", G29_PORT, 0, input_port, },
262 { "irq-7", G30_PORT, 0, input_port, },
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Ddv-mn103int.c223 { "ack", ACK_PORT, 0, input_port, },
227 { "nmirq", G0_PORT + 0, 0, input_port, },
256 { "irq-0", G23_PORT, 0, input_port, },
257 { "irq-1", G24_PORT, 0, input_port, },
258 { "irq-2", G25_PORT, 0, input_port, },
259 { "irq-3", G26_PORT, 0, input_port, },
260 { "irq-4", G27_PORT, 0, input_port, },
261 { "irq-5", G28_PORT, 0, input_port, },
262 { "irq-6", G29_PORT, 0, input_port, },
263 { "irq-7", G30_PORT, 0, input_port, },
[all …]
/dports/devel/concurrentqueue/concurrentqueue-1.0.3-15-g0753496/benchmarks/tbb/internal/
H A D_flow_graph_trace_impl.h95 itt_make_task_group( ITT_DOMAIN_FLOW, input_port, FLOW_NODE, g, FLOW_GRAPH, t );
96 fgt_internal_create_input_port( input_port, input_port, FLOW_INPUT_PORT_0 );
102 itt_make_task_group( ITT_DOMAIN_FLOW, input_port, FLOW_NODE, g, FLOW_GRAPH, t );
103 fgt_internal_create_input_port( input_port, input_port, FLOW_INPUT_PORT_0 );
105 fgt_body( input_port, body );
128 static inline void fgt_node( string_index t, void *g, void *input_port, void *output_port ) {
130 fgt_internal_create_input_port( output_port, input_port, FLOW_INPUT_PORT_0 );
135 fgt_internal_create_input_port( output_port, input_port, FLOW_INPUT_PORT_0 );
140 fgt_node( t, g, input_port, output_port );
144 static inline void fgt_make_edge( void *output_port, void *input_port ) {
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/lib/rfnoc/
H A Dswitchboard_block_control.cpp76 for (size_t input_port = 0; input_port < _num_input_ports; input_port++) { in _register_props() local
78 PROP_KEY_OUTPUT_SELECT, 0, {res_source_info::USER, input_port})); in _register_props()
80 register_property(&_output_select.back(), [this, input_port]() { in _register_props()
81 int select_val = _output_select.at(input_port).get(); in _register_props()
86 REG_DEMUX_SELECT_ADDR, select_val, input_port); in _register_props()
99 for (size_t input_port = 0; input_port < _num_input_ports; input_port++) { in _update_forwarding_map() local
100 size_t linked_output_port = _output_select.at(input_port).get(); in _update_forwarding_map()
102 if (linked_input_port == input_port) { in _update_forwarding_map()
/dports/devel/avr-gdb/gdb-7.3.1/sim/mips/
H A Ddv-tx3904irc.c143 { "int1", INT1_PORT, 0, input_port, },
144 { "int2", INT2_PORT, 0, input_port, },
145 { "int3", INT3_PORT, 0, input_port, },
146 { "int4", INT4_PORT, 0, input_port, },
147 { "int5", INT5_PORT, 0, input_port, },
148 { "int6", INT6_PORT, 0, input_port, },
149 { "int7", INT7_PORT, 0, input_port, },
156 { "sio0", SIO0_PORT, 0, input_port, },
157 { "sio1", SIO1_PORT, 0, input_port, },
159 { "tmr0", TMR0_PORT, 0, input_port, },
[all …]
/dports/devel/gdb761/gdb-7.6.1/sim/mips/
H A Ddv-tx3904irc.c142 { "int1", INT1_PORT, 0, input_port, },
143 { "int2", INT2_PORT, 0, input_port, },
144 { "int3", INT3_PORT, 0, input_port, },
145 { "int4", INT4_PORT, 0, input_port, },
146 { "int5", INT5_PORT, 0, input_port, },
147 { "int6", INT6_PORT, 0, input_port, },
148 { "int7", INT7_PORT, 0, input_port, },
155 { "sio0", SIO0_PORT, 0, input_port, },
156 { "sio1", SIO1_PORT, 0, input_port, },
158 { "tmr0", TMR0_PORT, 0, input_port, },
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/mips/
H A Ddv-tx3904irc.c143 { "int1", INT1_PORT, 0, input_port, },
144 { "int2", INT2_PORT, 0, input_port, },
145 { "int3", INT3_PORT, 0, input_port, },
146 { "int4", INT4_PORT, 0, input_port, },
147 { "int5", INT5_PORT, 0, input_port, },
148 { "int6", INT6_PORT, 0, input_port, },
149 { "int7", INT7_PORT, 0, input_port, },
156 { "sio0", SIO0_PORT, 0, input_port, },
157 { "sio1", SIO1_PORT, 0, input_port, },
159 { "tmr0", TMR0_PORT, 0, input_port, },
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/mips/
H A Ddv-tx3904irc.c143 { "int1", INT1_PORT, 0, input_port, },
144 { "int2", INT2_PORT, 0, input_port, },
145 { "int3", INT3_PORT, 0, input_port, },
146 { "int4", INT4_PORT, 0, input_port, },
147 { "int5", INT5_PORT, 0, input_port, },
148 { "int6", INT6_PORT, 0, input_port, },
149 { "int7", INT7_PORT, 0, input_port, },
156 { "sio0", SIO0_PORT, 0, input_port, },
157 { "sio1", SIO1_PORT, 0, input_port, },
159 { "tmr0", TMR0_PORT, 0, input_port, },
[all …]
/dports/devel/onetbb/oneTBB-2021.4.0/test/tbb/
H A Dtest_composite_node.cpp127 …t_tuple = std::tie(ct, s, m_fxn, fxn, bc, tbb::flow::input_port<0>(j), lim, q, tbb::flow::input_po… in add_all_nodes()
309 tbb::flow::make_edge( s, tbb::flow::input_port<0>(a0) ); in test_adder()
310 tbb::flow::make_edge( c, tbb::flow::input_port<1>(a0) ); in test_adder()
312 tbb::flow::make_edge( c, tbb::flow::input_port<0>(a1) ); in test_adder()
313 tbb::flow::make_edge( c, tbb::flow::input_port<1>(a1) ); in test_adder()
449 …e(tbb::flow::input_port<0>(j), tbb::flow::input_port<1>(j), tbb::flow::input_port<2>(j), tbb::flow… in prefix_node()
488 tbb::flow::input_port<0>(p).try_put( offset ); in test_prefix()
489 tbb::flow::input_port<1>(p).try_put( offset + 1 ); in test_prefix()
490 tbb::flow::input_port<2>(p).try_put( offset + 2 ); in test_prefix()
491 tbb::flow::input_port<3>(p).try_put( offset + 3 ); in test_prefix()
[all …]

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