/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 502 struct rc_instruction * inst_add, in presub_replace_add() argument 511 assert(!(inst_add->U.I.SrcReg[1].Negate && inst_add->U.I.SrcReg[0].Negate)); in presub_replace_add() 513 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 587 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 593 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 601 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 616 rc_remove_instruction(inst_add); in peephole_add_presub_add() 671 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 206 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 207 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 208 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 209 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 211 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 229 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 231 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 364 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 366 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 370 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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H A D | radeon_compiler.c | 310 struct rc_instruction *inst_add; in rc_transform_fragment_face() local 315 inst_add->U.I.Opcode = RC_OPCODE_ADD; in rc_transform_fragment_face() 317 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_transform_fragment_face() 318 inst_add->U.I.DstReg.Index = tempregi; in rc_transform_fragment_face() 319 inst_add->U.I.DstReg.WriteMask = RC_MASK_X; in rc_transform_fragment_face() 321 inst_add->U.I.SrcReg[0].File = RC_FILE_NONE; in rc_transform_fragment_face() 322 inst_add->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_1111; in rc_transform_fragment_face() 324 inst_add->U.I.SrcReg[1].File = RC_FILE_INPUT; in rc_transform_fragment_face() 325 inst_add->U.I.SrcReg[1].Index = face; in rc_transform_fragment_face() 326 inst_add->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XXXX; in rc_transform_fragment_face() [all …]
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/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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H A D | radeon_compiler.c | 326 struct rc_instruction *inst_add; in rc_transform_fragment_face() local 331 inst_add->U.I.Opcode = RC_OPCODE_ADD; in rc_transform_fragment_face() 333 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_transform_fragment_face() 334 inst_add->U.I.DstReg.Index = tempregi; in rc_transform_fragment_face() 335 inst_add->U.I.DstReg.WriteMask = RC_MASK_X; in rc_transform_fragment_face() 337 inst_add->U.I.SrcReg[0].File = RC_FILE_NONE; in rc_transform_fragment_face() 338 inst_add->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_1111; in rc_transform_fragment_face() 340 inst_add->U.I.SrcReg[1].File = RC_FILE_INPUT; in rc_transform_fragment_face() 341 inst_add->U.I.SrcReg[1].Index = face; in rc_transform_fragment_face() 342 inst_add->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XXXX; in rc_transform_fragment_face() [all …]
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/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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H A D | radeon_compiler.c | 326 struct rc_instruction *inst_add; in rc_transform_fragment_face() local 331 inst_add->U.I.Opcode = RC_OPCODE_ADD; in rc_transform_fragment_face() 333 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_transform_fragment_face() 334 inst_add->U.I.DstReg.Index = tempregi; in rc_transform_fragment_face() 335 inst_add->U.I.DstReg.WriteMask = RC_MASK_X; in rc_transform_fragment_face() 337 inst_add->U.I.SrcReg[0].File = RC_FILE_NONE; in rc_transform_fragment_face() 338 inst_add->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_1111; in rc_transform_fragment_face() 340 inst_add->U.I.SrcReg[1].File = RC_FILE_INPUT; in rc_transform_fragment_face() 341 inst_add->U.I.SrcReg[1].Index = face; in rc_transform_fragment_face() 342 inst_add->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XXXX; in rc_transform_fragment_face() [all …]
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 471 struct rc_instruction * inst_add, in presub_helper() argument 504 struct rc_instruction * inst_add, in presub_replace_add() argument 509 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 583 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 589 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 593 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 597 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 612 rc_remove_instruction(inst_add); in peephole_add_presub_add() 619 struct rc_instruction * inst_add, in presub_replace_inv() argument 667 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/r300/compiler/ |
H A D | radeon_optimize.c | 469 struct rc_instruction * inst_add, in presub_helper() argument 502 struct rc_instruction * inst_add, in presub_replace_add() argument 507 if (inst_add->U.I.SrcReg[1].Negate || inst_add->U.I.SrcReg[0].Negate) in presub_replace_add() 581 struct rc_instruction * inst_add) in peephole_add_presub_add() argument 587 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle) in peephole_add_presub_add() 591 if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs) in peephole_add_presub_add() 595 if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate) in peephole_add_presub_add() 610 rc_remove_instruction(inst_add); in peephole_add_presub_add() 617 struct rc_instruction * inst_add, in presub_replace_inv() argument 664 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv() [all …]
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H A D | radeon_program_tex.c | 207 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 208 inst_add->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX() 209 inst_add->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX() 210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX() 212 inst_add->U.I.SrcReg[0].Index = tmp_sum; in radeonTransformTEX() 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX() 365 inst_add->U.I.Opcode = RC_OPCODE_ADD; in radeonTransformTEX() 367 inst_add->U.I.DstReg.Index = temp; in radeonTransformTEX() 371 inst_add->U.I.SrcReg[1].Index = temp; in radeonTransformTEX() [all …]
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