| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/mlir/lib/Dialect/VectorOps/ |
| H A D | VectorTransforms.cpp | 258 bool isAcc = false; member
417 vectors[i].isAcc = i == accOperandIndex ? true : false; in getVectorContractionOpUnrollState()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/mlir/lib/Dialect/Vector/ |
| H A D | VectorTransforms.cpp | 312 bool isAcc = false; member
465 vectors[i].isAcc = i == accOperandIndex ? true : false; in getVectorContractionOpUnrollState()
|
| /dports/security/py-pyvex/pyvex-9.0.5405/vex/priv/ |
| H A D | guest_arm64_toIR.c | 9376 Bool isAcc = opcode == BITS5(0,0,0,1,0);
9393 assign(res, isAcc ? binop(Iop_Add64x2, getQReg128(dd), mkexpr(shf))
9396 const HChar* nm = isAcc ? (isU ? "usra" : "ssra")
9409 Bool isAcc = opcode == BITS5(0,0,1,1,0);
9421 assign(res, isAcc ? binop(Iop_Add64x2, getQReg128(dd), mkexpr(shf))
9424 const HChar* nm = isAcc ? (isU ? "ursra" : "srsra")
10569 Bool isAcc = opcode == BITS5(0,0,0,1,0);
10589 assign(res, isAcc ? binop(mkVecADD(size), getQReg128(dd), mkexpr(shf))
10594 const HChar* nm = isAcc ? (isU ? "usra" : "ssra")
10618 Bool isAcc = opcode == BITS5(0,0,1,1,0);
[all …]
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| /dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/VEX/priv/ |
| H A D | guest_arm64_toIR.c | 9533 Bool isAcc = opcode == BITS5(0,0,0,1,0); in dis_AdvSIMD_scalar_shift_by_imm() local
9550 assign(res, isAcc ? binop(Iop_Add64x2, getQReg128(dd), mkexpr(shf)) in dis_AdvSIMD_scalar_shift_by_imm()
9553 const HChar* nm = isAcc ? (isU ? "usra" : "ssra") in dis_AdvSIMD_scalar_shift_by_imm()
9566 Bool isAcc = opcode == BITS5(0,0,1,1,0); in dis_AdvSIMD_scalar_shift_by_imm() local
9578 assign(res, isAcc ? binop(Iop_Add64x2, getQReg128(dd), mkexpr(shf)) in dis_AdvSIMD_scalar_shift_by_imm()
9581 const HChar* nm = isAcc ? (isU ? "ursra" : "srsra") in dis_AdvSIMD_scalar_shift_by_imm()
10726 Bool isAcc = opcode == BITS5(0,0,0,1,0); in dis_AdvSIMD_shift_by_immediate() local
10746 assign(res, isAcc ? binop(mkVecADD(size), getQReg128(dd), mkexpr(shf)) in dis_AdvSIMD_shift_by_immediate()
10751 const HChar* nm = isAcc ? (isU ? "usra" : "ssra") in dis_AdvSIMD_shift_by_immediate()
10775 Bool isAcc = opcode == BITS5(0,0,1,1,0); in dis_AdvSIMD_shift_by_immediate() local
[all …]
|
| /dports/devel/valgrind/valgrind-dragonfly-dragonfly/VEX/priv/ |
| H A D | guest_arm64_toIR.c | 9533 Bool isAcc = opcode == BITS5(0,0,0,1,0); in dis_AdvSIMD_scalar_shift_by_imm() local
9550 assign(res, isAcc ? binop(Iop_Add64x2, getQReg128(dd), mkexpr(shf)) in dis_AdvSIMD_scalar_shift_by_imm()
9553 const HChar* nm = isAcc ? (isU ? "usra" : "ssra") in dis_AdvSIMD_scalar_shift_by_imm()
9566 Bool isAcc = opcode == BITS5(0,0,1,1,0); in dis_AdvSIMD_scalar_shift_by_imm() local
9578 assign(res, isAcc ? binop(Iop_Add64x2, getQReg128(dd), mkexpr(shf)) in dis_AdvSIMD_scalar_shift_by_imm()
9581 const HChar* nm = isAcc ? (isU ? "ursra" : "srsra") in dis_AdvSIMD_scalar_shift_by_imm()
10726 Bool isAcc = opcode == BITS5(0,0,0,1,0); in dis_AdvSIMD_shift_by_immediate() local
10746 assign(res, isAcc ? binop(mkVecADD(size), getQReg128(dd), mkexpr(shf)) in dis_AdvSIMD_shift_by_immediate()
10751 const HChar* nm = isAcc ? (isU ? "usra" : "ssra") in dis_AdvSIMD_shift_by_immediate()
10775 Bool isAcc = opcode == BITS5(0,0,1,1,0); in dis_AdvSIMD_shift_by_immediate() local
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/mlir/lib/Dialect/Vector/ |
| H A D | VectorTransforms.cpp | 318 bool isAcc = false; member
471 vectors[i].isAcc = i == accOperandIndex ? true : false; in getVectorContractionOpUnrollState()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/mlir/lib/Dialect/Vector/ |
| H A D | VectorTransforms.cpp | 317 bool isAcc = false; member
470 vectors[i].isAcc = i == accOperandIndex ? true : false; in getVectorContractionOpUnrollState()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/mlir/lib/Dialect/Vector/ |
| H A D | VectorTransforms.cpp | 317 bool isAcc = false; member
470 vectors[i].isAcc = i == accOperandIndex ? true : false; in getVectorContractionOpUnrollState()
|