| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
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| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
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| H A D | HexagonInstrInfo.cpp | 4328 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const { in isPureSlot0() function in HexagonInstrInfo
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| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
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| H A D | HexagonInstrInfo.cpp | 4325 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const { in isPureSlot0() function in HexagonInstrInfo
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| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const; in _expand_delta()
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| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
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| H A D | HexagonInstrInfo.cpp | 4328 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const { in isPureSlot0() function in HexagonInstrInfo
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 392 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
1875 isSlot0Only |= HII->isPureSlot0(*J); in isPureSlot0InsnWithNoSlot1Store()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 391 bool isPureSlot0(const MachineInstr &MI) const;
|
| H A D | HexagonVLIWPacketizer.cpp | 1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ);
1875 isSlot0Only |= HII->isPureSlot0(*J);
|