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Searched refs:ivl_logic_type (Results 1 – 19 of 19) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vvp/
H A Ddraw_net_input.c177 if (ivl_logic_type(logic) == IVL_LO_BUFIF0) in nexus_drive_is_strength_aware()
179 if (ivl_logic_type(logic) == IVL_LO_BUFIF1) in nexus_drive_is_strength_aware()
181 if (ivl_logic_type(logic) == IVL_LO_PMOS) in nexus_drive_is_strength_aware()
183 if (ivl_logic_type(logic) == IVL_LO_NMOS) in nexus_drive_is_strength_aware()
185 if (ivl_logic_type(logic) == IVL_LO_CMOS) in nexus_drive_is_strength_aware()
293 && ((ivl_logic_type(lptr)==IVL_LO_BUFZ)||(ivl_logic_type(lptr)==IVL_LO_BUFT)) in draw_net_input_drive()
302 if (lptr && (ivl_logic_type(lptr) == IVL_LO_PULLDOWN)) { in draw_net_input_drive()
306 if (lptr && (ivl_logic_type(lptr) == IVL_LO_PULLUP)) { in draw_net_input_drive()
H A Dvvp_scope.c369 (ivl_logic_type(net) == IVL_LO_BUFZ)) { in can_elide_bufz()
928 if (ivl_logic_type(lptr) == IVL_LO_EQUIV) { in draw_equiv_impl_in_scope()
931 assert(ivl_logic_type(lptr) == IVL_LO_IMPL); in draw_equiv_impl_in_scope()
957 switch (ivl_logic_type(lptr)) { in draw_logic_in_scope()
1082 ivl_logic_type(lptr)); in draw_logic_in_scope()
/dports/cad/iverilog/verilog-11.0/tgt-sizer/
H A Dscan_logs.cc34 switch (ivl_logic_type(log)) { in scan_logs()
51 stats.log_bytype[ivl_logic_type(log)] += 1; in scan_logs()
/dports/cad/iverilog/verilog-11.0/tgt-blif/
H A Dlogic_gate.cc57 switch (ivl_logic_type(net)) { in do_print_logic_gate()
114 fprintf(fd, "# ERROR: Logic type %d not handled\n", ivl_logic_type(net)); in do_print_logic_gate()
/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dlogic.cc233 switch (ivl_logic_type(log)) { in translate_logic_inputs()
258 ivl_logic_type(log)); in translate_logic_inputs()
265 switch (ivl_logic_type(log)) { in draw_logic()
/dports/cad/iverilog/verilog-11.0/tgt-pal/
H A Denables.c47 switch (ivl_logic_type(log)) { in absorb_pad_enable()
/dports/cad/iverilog/verilog-11.0/tgt-fpga/
H A Dd-generic-edif.c299 switch (ivl_logic_type(net)) { in edif_show_logic()
381 fprintf(stderr, "UNSUPPORT LOGIC TYPE: %d\n", ivl_logic_type(net)); in edif_show_logic()
H A Dd-generic.c126 switch (ivl_logic_type(net)) { in generic_show_logic()
250 ivl_logic_type(net)); in generic_show_logic()
H A Dd-virtex.c82 if (ivl_logic_type(net) == IVL_LO_OR) { in virtex_or_wide()
222 switch (ivl_logic_type(net)) { in virtex_logic()
H A Dd-lpm.c321 switch (ivl_logic_type(net)) { in lpm_logic()
400 ivl_logic_type(net)); in lpm_logic()
H A Dxilinx.c603 switch (ivl_logic_type(net)) { in xilinx_logic()
698 ivl_logic_type(net)); in xilinx_logic()
/dports/cad/iverilog/verilog-11.0/tgt-vlog95/
H A Dlogic_lpm.c70 if (ivl_logic_type(t_nlogic) == IVL_LO_BUFZ) { in nexus_driver_is_signed()
682 switch (ivl_logic_type(nlogic)) { in emit_logic_as_ca()
772 (int)ivl_logic_type(nlogic)); in emit_logic_as_ca()
897 if (ivl_logic_type(t_nlogic) == IVL_LO_BUFZ) { in nexus_is_signal()
1947 if (ivl_logic_type(nlogic) != IVL_LO_UDP) { in emit_name_of_logic_nexus()
1952 ivl_logic_type(nlogic), in emit_name_of_logic_nexus()
1977 if (ivl_logic_type(nlogic) != IVL_LO_NOT) pin_count += 1; in emit_logic()
1995 switch (ivl_logic_type(nlogic)) { in emit_logic()
2095 ivl_logic_lineno(nlogic), ivl_logic_type(nlogic), in emit_logic()
2386 ivl_logic_t logic_type = ivl_logic_type(nlogic); in dump_nexus_information()
[all …]
H A Dmisc.c747 if (nlogic && ivl_logic_type(nlogic) == IVL_LO_BUFT in emit_name_of_nexus()
/dports/cad/iverilog/verilog-11.0/
H A Divl.def107 ivl_logic_type
H A Divl_target.h1098 extern ivl_logic_t ivl_logic_type(ivl_net_logic_t net);
H A Dcppcheck.sup197 //ivl_logic_type()
H A Dt-dll-api.cc940 extern "C" ivl_logic_t ivl_logic_type(ivl_net_logic_t net) in ivl_logic_type() function
/dports/cad/iverilog/verilog-11.0/tgt-verilog/
H A Dverilog.c110 switch (ivl_logic_type(net)) { in draw_logic()
/dports/cad/iverilog/verilog-11.0/tgt-stub/
H A Dstub.c1538 switch (ivl_logic_type(net)) { in show_logic()
1612 fprintf(out, " unsupported gate<type=%d> %s", ivl_logic_type(net), name); in show_logic()
1664 if (ivl_logic_type(net) == IVL_LO_UDP) { in show_logic()