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Searched refs:ivl_stmt_cond_expr (Results 1 – 9 of 9) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-stub/
H A Dstatement.c396 show_expression(ivl_stmt_cond_expr(net), ind+4); in show_statement()
418 ivl_expr_t ex = ivl_stmt_cond_expr(net); in show_statement()
474 show_expression(ivl_stmt_cond_expr(net), ind+4); in show_statement()
550 show_expression(ivl_stmt_cond_expr(net), ind+4); in show_statement()
/dports/cad/iverilog/verilog-11.0/tgt-vlog95/
H A Dstmt.c63 ivl_expr_t count = ivl_stmt_cond_expr(stmt); in emit_stmt_inter_delay()
525 emit_expr(scope, ivl_stmt_cond_expr(while_lp), 0, 0, 0, 0); in is_for_loop()
603 emit_expr(scope, ivl_stmt_cond_expr(repeat), 0, 0, 0, 0); in is_repeat_event_assign()
642 while_expr = ivl_stmt_cond_expr(while_wait); in is_wait()
978 emit_expr(scope, ivl_stmt_cond_expr(stmt), 0, 0, 0, 0); in emit_stmt_case()
1028 emit_expr(scope, ivl_stmt_cond_expr(stmt), 0, 0, 0, 0); in emit_stmt_condit()
1302 emit_expr(scope, ivl_stmt_cond_expr(stmt), 0, 0, 0, 0); in emit_stmt_do_while()
1314 emit_expr(scope, ivl_stmt_cond_expr(stmt), 0, 0, 0, 0); in emit_stmt_do_while()
1390 emit_expr(scope, ivl_stmt_cond_expr(stmt), 0, 0, 0, 0); in emit_stmt_repeat()
1484 emit_expr(scope, ivl_stmt_cond_expr(stmt), 0, 0, 0, 0); in emit_stmt_while()
/dports/cad/iverilog/verilog-11.0/tgt-vvp/
H A Dvvp_process.c489 ivl_expr_t cnt = ivl_stmt_cond_expr(net); in show_stmt_assign_nb()
527 assert(ivl_stmt_cond_expr(net) == 0); in show_stmt_assign_nb()
648 ivl_expr_t expr = ivl_stmt_cond_expr(net); in show_stmt_case()
769 ivl_expr_t expr = ivl_stmt_cond_expr(net); in show_stmt_case_r()
1230 ivl_expr_t expr = ivl_stmt_cond_expr(net); in show_stmt_condit()
1367 int use_flag = draw_eval_condition(ivl_stmt_cond_expr(net)); in show_stmt_do_while()
1601 ivl_expr_t expr = ivl_stmt_cond_expr(net); in show_stmt_repeat()
1730 int use_flag = draw_eval_condition(ivl_stmt_cond_expr(net)); in show_stmt_while()
2053 while_expr = ivl_stmt_cond_expr(while_wait); in is_wait()
/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dstmt.cc772 get_nexuses_from_expr(ivl_stmt_cond_expr(sub_stmt), test_nexuses); in draw_synthesisable_wait()
791 vhdl_expr *reset_test = translate_expr(ivl_stmt_cond_expr(sub_stmt)); in draw_synthesisable_wait()
1029 vhdl_expr *test = translate_expr(ivl_stmt_cond_expr(stmt)); in draw_if()
1052 vhdl_expr *test = translate_expr(ivl_stmt_cond_expr(stmt)); in draw_case_test()
1563 vhdl_expr *test = translate_expr(ivl_stmt_cond_expr(stmt)); in draw_while()
1597 vhdl_expr *times = translate_expr(ivl_stmt_cond_expr(stmt)); in draw_repeat()
/dports/cad/iverilog/verilog-11.0/
H A Divl.def286 ivl_stmt_cond_expr
H A Divl_target.h2245 extern ivl_expr_t ivl_stmt_cond_expr(ivl_statement_t net);
H A Dcppcheck.sup514 //ivl_stmt_cond_expr()
H A Dt-dll-api.cc2766 extern "C" ivl_expr_t ivl_stmt_cond_expr(ivl_statement_t net) in ivl_stmt_cond_expr() function
/dports/cad/iverilog/verilog-11.0/tgt-verilog/
H A Dverilog.c328 show_expression(ivl_stmt_cond_expr(net)); in show_statement()