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Searched refs:ivl_stmt_nevent (Results 1 – 9 of 9) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-stub/
H A Dstatement.c255 unsigned cnt = ivl_stmt_nevent(net); in show_stmt_trigger()
285 if ((ivl_stmt_nevent(net) == 1) && (ivl_stmt_events(net, 0) == 0)) { in show_stmt_wait()
293 for (idx = 0 ; idx < ivl_stmt_nevent(net) ; idx += 1) { in show_stmt_wait()
/dports/cad/iverilog/verilog-11.0/tgt-vlog95/
H A Devent.c46 nevents = ivl_stmt_nevent(stmt); in emit_event()
H A Dstmt.c61 unsigned nevents = ivl_stmt_nevent(stmt); in emit_stmt_inter_delay()
1423 assert(ivl_stmt_nevent(stmt) == 1); in emit_stmt_trigger()
1457 if (ivl_stmt_nevent(stmt) != 1) return 0; in is_wait_fork()
/dports/cad/iverilog/verilog-11.0/
H A Divl.def300 ivl_stmt_nevent
H A Divl_target.h2256 extern unsigned ivl_stmt_nevent(ivl_statement_t net);
H A Dcppcheck.sup540 //ivl_stmt_nevent()
H A Dt-dll-api.cc2847 extern "C" unsigned ivl_stmt_nevent(ivl_statement_t net) in ivl_stmt_nevent() function
/dports/cad/iverilog/verilog-11.0/tgt-vvp/
H A Dvvp_process.c415 unsigned nevents = ivl_stmt_nevent(net); in show_stmt_assign_nb_real()
481 unsigned nevents = ivl_stmt_nevent(net); in show_stmt_assign_nb()
1672 if ((ivl_stmt_nevent(net) == 1) && (ivl_stmt_events(net, 0) == 0)) { in show_stmt_wait()
1681 if (ivl_stmt_nevent(net) == 0) { in show_stmt_wait()
1684 } else if (ivl_stmt_nevent(net) == 1) { in show_stmt_wait()
1700 for (idx = 1 ; idx < ivl_stmt_nevent(net) ; idx += 1) { in show_stmt_wait()
/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dstmt.cc736 const int nevents = ivl_stmt_nevent(stmt); in draw_synthesisable_wait()
909 int nevents = ivl_stmt_nevent(stmt); in draw_wait()