| /dports/graphics/cfdg/cfdg-3.3_1/src-scintilla/lexers/ |
| H A D | LexVerilog.cxx | 405 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
531 lineState = kwInput; in Lex()
539 } else if (lineState == kwInput) { in Lex()
|
| /dports/x11-toolkits/wxgtk31/wxWidgets-3.1.5/src/stc/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 398 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
524 lineState = kwInput; in Lex()
532 } else if (lineState == kwInput) { in Lex()
|
| /dports/x11-toolkits/scintilla/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 405 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
531 lineState = kwInput; in Lex()
539 } else if (lineState == kwInput) { in Lex()
|
| /dports/devel/codequery/codequery-0.24.0/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 401 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
527 lineState = kwInput; in Lex()
535 } else if (lineState == kwInput) { in Lex()
|
| /dports/devel/codeblocks/codeblocks-20.03/src/sdk/wxscintilla/src/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 398 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
524 lineState = kwInput; in Lex()
532 } else if (lineState == kwInput) { in Lex()
|
| /dports/devel/geany-legacy/geany-1.37.1/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 405 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
531 lineState = kwInput; in Lex()
539 } else if (lineState == kwInput) { in Lex()
|
| /dports/devel/geany/geany-1.38/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 405 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
531 lineState = kwInput; in Lex()
539 } else if (lineState == kwInput) { in Lex()
|
| /dports/editors/textadept/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 405 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
531 lineState = kwInput; in Lex()
539 } else if (lineState == kwInput) { in Lex()
|
| /dports/editors/scite/scintilla/lexers/ |
| H A D | LexVerilog.cxx | 405 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
531 lineState = kwInput; in Lex()
539 } else if (lineState == kwInput) { in Lex()
|
| /dports/devel/qscintilla2-qt5/QScintilla_src-2.13.0/scintilla/lexers/ |
| H A D | LexVerilog.cpp | 401 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
527 lineState = kwInput; in Lex()
535 } else if (lineState == kwInput) { in Lex()
|
| /dports/devel/qscintilla2-designerplugin-qt5/QScintilla_src-2.13.0/scintilla/lexers/ |
| H A D | LexVerilog.cpp | 401 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
527 lineState = kwInput; in Lex()
535 } else if (lineState == kwInput) { in Lex()
|
| /dports/devel/py-qt5-qscintilla2/QScintilla_src-2.13.0/scintilla/lexers/ |
| H A D | LexVerilog.cpp | 401 const int kwOther=0, kwDot=0x100, kwInput=0x200, kwOutput=0x300, kwInout=0x400, kwProtected=0x800; in Lex() local
527 lineState = kwInput; in Lex()
535 } else if (lineState == kwInput) { in Lex()
|