/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
H A D | asimd-ld3.s | 6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label 8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label 10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label 12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label 14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label 16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label 18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label 22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label 24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label 26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label [all …]
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/dports/devel/ga/ga-5.8/global/testing/ |
H A D | g2test.F | 46 integer dims3(7), ld3(7), chunk(7) 238 + index3, ld3) 267 + call aprint(int_mb(index3),dims3(1),dims3(2),ld3,has_data) 269 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 302 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 335 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 372 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 411 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 445 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 479 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, [all …]
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H A D | ghosts.F | 171 integer dims3(7), ld3(7), chunk(7) local 342 + index3, ld3) 371 + call aprint(int_mb(index3),dims3(1),dims3(2),ld3,has_data) 373 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 404 + call aprint(int_mb(index3),dims3(1),dims3(2),ld3,has_data) 406 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 439 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 476 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 515 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, 549 call atest(int_mb(index3),dims3(1),dims3(2),ld3,b, [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 84 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 85 ; CHECK-LABEL: ld3.nxv48i8: 94 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 95 ; CHECK-LABEL: ld3.nxv24i16: 104 ; CHECK-LABEL: ld3.nxv24f16: 113 ; CHECK-LABEL: ld3.nxv24bf16: 123 ; CHECK-LABEL: ld3.nxv12i32: 132 ; CHECK-LABEL: ld3.nxv12f32: 141 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 142 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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H A D | sve-intrinsics-ldN-reg+imm-addr-mode.ll | 152 ; CHECK-LABEL: ld3.nxv48i8: 162 ; CHECK-LABEL: ld3.nxv48i8_lower_bound: 172 ; CHECK-LABEL: ld3.nxv48i8_upper_bound: 204 ; CHECK-LABEL: ld3.nxv48i8_outside_lower_bound: 227 ; CHECK-LABEL: ld3.nxv24i16: 237 ; CHECK-LABEL: ld3.nxv24f16: 247 ; CHECK-LABEL: ld3.nxv24bf16: 258 ; CHECK-LABEL: ld3.nxv12i32: 268 ; CHECK-LABEL: ld3.nxv12f32: 279 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 80 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 81 ; CHECK-LABEL: ld3.nxv48i8: 90 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 91 ; CHECK-LABEL: ld3.nxv24i16: 100 ; CHECK-LABEL: ld3.nxv24f16: 109 ; CHECK-LABEL: ld3.nxv24bf16: 119 ; CHECK-LABEL: ld3.nxv12i32: 128 ; CHECK-LABEL: ld3.nxv12f32: 137 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 138 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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H A D | sve-intrinsics-ldN-reg+imm-addr-mode.ll | 148 ; CHECK-LABEL: ld3.nxv48i8: 158 ; CHECK-LABEL: ld3.nxv48i8_lower_bound: 168 ; CHECK-LABEL: ld3.nxv48i8_upper_bound: 200 ; CHECK-LABEL: ld3.nxv48i8_outside_lower_bound: 223 ; CHECK-LABEL: ld3.nxv24i16: 233 ; CHECK-LABEL: ld3.nxv24f16: 243 ; CHECK-LABEL: ld3.nxv24bf16: 254 ; CHECK-LABEL: ld3.nxv12i32: 264 ; CHECK-LABEL: ld3.nxv12f32: 275 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 80 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 81 ; CHECK-LABEL: ld3.nxv48i8: 90 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 91 ; CHECK-LABEL: ld3.nxv24i16: 100 ; CHECK-LABEL: ld3.nxv24f16: 109 ; CHECK-LABEL: ld3.nxv24bf16: 119 ; CHECK-LABEL: ld3.nxv12i32: 128 ; CHECK-LABEL: ld3.nxv12f32: 137 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 138 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 84 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 85 ; CHECK-LABEL: ld3.nxv48i8: 94 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 95 ; CHECK-LABEL: ld3.nxv24i16: 104 ; CHECK-LABEL: ld3.nxv24f16: 113 ; CHECK-LABEL: ld3.nxv24bf16: 123 ; CHECK-LABEL: ld3.nxv12i32: 132 ; CHECK-LABEL: ld3.nxv12f32: 141 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 142 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 80 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 81 ; CHECK-LABEL: ld3.nxv48i8: 90 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 91 ; CHECK-LABEL: ld3.nxv24i16: 100 ; CHECK-LABEL: ld3.nxv24f16: 109 ; CHECK-LABEL: ld3.nxv24bf16: 119 ; CHECK-LABEL: ld3.nxv12i32: 128 ; CHECK-LABEL: ld3.nxv12f32: 137 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 138 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 80 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 81 ; CHECK-LABEL: ld3.nxv48i8: 90 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 91 ; CHECK-LABEL: ld3.nxv24i16: 100 ; CHECK-LABEL: ld3.nxv24f16: 109 ; CHECK-LABEL: ld3.nxv24bf16: 119 ; CHECK-LABEL: ld3.nxv12i32: 128 ; CHECK-LABEL: ld3.nxv12f32: 137 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 138 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 80 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 81 ; CHECK-LABEL: ld3.nxv48i8: 90 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 91 ; CHECK-LABEL: ld3.nxv24i16: 100 ; CHECK-LABEL: ld3.nxv24f16: 109 ; CHECK-LABEL: ld3.nxv24bf16: 119 ; CHECK-LABEL: ld3.nxv12i32: 128 ; CHECK-LABEL: ld3.nxv12f32: 137 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 138 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 84 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 85 ; CHECK-LABEL: ld3.nxv48i8: 94 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 95 ; CHECK-LABEL: ld3.nxv24i16: 104 ; CHECK-LABEL: ld3.nxv24f16: 113 ; CHECK-LABEL: ld3.nxv24bf16: 123 ; CHECK-LABEL: ld3.nxv12i32: 132 ; CHECK-LABEL: ld3.nxv12f32: 141 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 142 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 80 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) { 81 ; CHECK-LABEL: ld3.nxv48i8: 90 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) { 91 ; CHECK-LABEL: ld3.nxv24i16: 100 ; CHECK-LABEL: ld3.nxv24f16: 109 ; CHECK-LABEL: ld3.nxv24bf16: 119 ; CHECK-LABEL: ld3.nxv12i32: 128 ; CHECK-LABEL: ld3.nxv12f32: 137 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) { 138 ; CHECK-LABEL: ld3.nxv6i64: [all …]
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