Searched refs:logic_out (Results 1 – 6 of 6) sorted by relevance
/dports/cad/verilator/verilator-4.216/test_regress/t/ |
H A D | t_stream_integer_type.v | 82 test_short logic_out[4]; register 135 {<<16{logic_out}} = v_packed_data_64; 167 {<<test_short{logic_out}} = v_packed_data_64; 230 … foreach (logic_in[i]) $display("logic_in[%0d]=%0h, logic_out=%0h", i, logic_in[i], logic_out[i]); 261 …(logic_in[i]) $display(" %s logic_in[%0d]=%0h, logic_out=%0h", name, i, logic_in[i], logic_out[i]); 323 …if (error_ == "") foreach (logic_in[i]) if (logic_in[i] !== logic_out[i]) error_ = "integer_vector…
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H A D | t_stream_integer_type.out | 69 135 | {<<16{logic_out}} = v_packed_data_64;
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/dports/biology/avida/avida-2.12.4-src/avida-core/source/main/ |
H A D | cTaskLib.cc | 392 logic_out[1] = logic_out[0]; in SetupTests() 395 logic_out[2] = logic_out[0]; in SetupTests() 396 logic_out[3] = logic_out[1]; in SetupTests() 399 logic_out[4] = logic_out[0]; in SetupTests() 400 logic_out[5] = logic_out[1]; in SetupTests() 401 logic_out[6] = logic_out[2]; in SetupTests() 402 logic_out[7] = logic_out[3]; in SetupTests() 406 assert(logic_out[0] >= 0 && logic_out[0] <= 1); in SetupTests() 407 assert(logic_out[1] >= 0 && logic_out[1] <= 1); in SetupTests() 408 assert(logic_out[2] >= 0 && logic_out[2] <= 1); in SetupTests() [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/lib/ |
H A D | logic_pio.c | 254 void logic_out##bwl(type value, unsigned long addr) \
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/dports/multimedia/libv4l/linux-5.13-rc2/lib/ |
H A D | logic_pio.c | 254 void logic_out##bwl(type value, unsigned long addr) \
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/dports/multimedia/v4l-utils/linux-5.13-rc2/lib/ |
H A D | logic_pio.c | 254 void logic_out##bwl(type value, unsigned long addr) \
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