Searched refs:m_user_clk (Results 1 – 4 of 4) sorted by relevance
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/sim/aurora_loopback/ |
| H A D | aurora_loopback_tb.sv | 40 wire m_user_clk, s_user_clk; net
77 .user_clk(m_user_clk),
196 @(posedge m_user_clk);
200 @(posedge m_user_clk);
202 repeat (512) @(posedge m_user_clk);
205 @(posedge m_user_clk);
207 repeat (256) @(posedge m_user_clk);
284 @(posedge m_user_clk);
288 @(posedge m_user_clk);
290 repeat (512) @(posedge m_user_clk);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/ |
| H A D | arm_to_sfp_tb.sv | 42 wire m_user_clk, s_user_clk; net
97 assign m_user_clk = independent_clock;
109 axis_master #(.DWIDTH(34)) m_axis (.clk(m_user_clk));
186 .sys_clk(m_user_clk),
216 .clk(m_user_clk),
231 .clk (m_user_clk),
247 (.clk(m_user_clk), .reset(GSR), .clear(clear),
344 while (m_channel_up !== 1'b1) @(posedge m_user_clk);
351 repeat(2000) @(posedge m_user_clk);
466 repeat(2000) @(posedge m_user_clk);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/ |
| H A D | one_gig_eth_loopback_tb.sv | 41 wire m_user_clk, s_user_clk; net
60 assign m_user_clk = independent_clock;
72 cvita_master m_tx_chdr (.clk(m_user_clk));
94 .clk (m_user_clk),
169 .sys_clk(m_user_clk),
263 while (m_channel_up !== 1'b1) @(posedge m_user_clk);
286 repeat(1000) @(posedge m_user_clk);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ |
| H A D | ten_gig_eth_loopback_tb.sv | 42 wire m_user_clk, s_user_clk; net
94 assign m_user_clk = independent_clock;
106 cvita_master m_tx_chdr (.clk(m_user_clk));
187 .sys_clk(m_user_clk),
348 while (m_channel_up !== 1'b1) @(posedge m_user_clk);
371 repeat(2000) @(posedge m_user_clk);
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