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Searched refs:mask_regs (Results 1 – 25 of 39) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/include/linux/
H A Dsh_intc.h88 struct intc_mask_reg *mask_regs; member
102 #define INTC_HW_DESC(vectors, groups, mask_regs, \ argument
106 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
121 mask_regs, prio_regs, sense_regs) \ argument
124 .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
129 mask_regs, prio_regs, sense_regs, ack_regs) \ argument
132 .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
/dports/multimedia/v4l_compat/linux-5.13-rc2/include/linux/
H A Dsh_intc.h88 struct intc_mask_reg *mask_regs; member
102 #define INTC_HW_DESC(vectors, groups, mask_regs, \ argument
106 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
121 mask_regs, prio_regs, sense_regs) \ argument
124 .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
129 mask_regs, prio_regs, sense_regs, ack_regs) \ argument
132 .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
/dports/multimedia/v4l-utils/linux-5.13-rc2/include/linux/
H A Dsh_intc.h88 struct intc_mask_reg *mask_regs; member
102 #define INTC_HW_DESC(vectors, groups, mask_regs, \ argument
106 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
121 mask_regs, prio_regs, sense_regs) \ argument
124 .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
129 mask_regs, prio_regs, sense_regs, ack_regs) \ argument
132 .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/mfd/
H A Dpcf50633-irq.c64 pcf->mask_regs[idx] |= bit; in __pcf50633_irq_mask_set()
66 pcf->mask_regs[idx] &= ~bit; in __pcf50633_irq_mask_set()
96 return pcf->mask_regs[reg] & bits; in pcf50633_irq_mask_get()
181 if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) in pcf50633_irq()
187 if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) in pcf50633_irq()
210 pcf_int[i] &= ~pcf->mask_regs[i]; in pcf50633_irq()
285 pcf->mask_regs[0] = 0x80; in pcf50633_irq_init()
286 pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); in pcf50633_irq_init()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/mfd/
H A Dpcf50633-irq.c64 pcf->mask_regs[idx] |= bit; in __pcf50633_irq_mask_set()
66 pcf->mask_regs[idx] &= ~bit; in __pcf50633_irq_mask_set()
96 return pcf->mask_regs[reg] & bits; in pcf50633_irq_mask_get()
181 if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) in pcf50633_irq()
187 if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) in pcf50633_irq()
210 pcf_int[i] &= ~pcf->mask_regs[i]; in pcf50633_irq()
285 pcf->mask_regs[0] = 0x80; in pcf50633_irq_init()
286 pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); in pcf50633_irq_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/mfd/
H A Dpcf50633-irq.c64 pcf->mask_regs[idx] |= bit; in __pcf50633_irq_mask_set()
66 pcf->mask_regs[idx] &= ~bit; in __pcf50633_irq_mask_set()
96 return pcf->mask_regs[reg] & bits; in pcf50633_irq_mask_get()
181 if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) in pcf50633_irq()
187 if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) in pcf50633_irq()
210 pcf_int[i] &= ~pcf->mask_regs[i]; in pcf50633_irq()
285 pcf->mask_regs[0] = 0x80; in pcf50633_irq_init()
286 pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); in pcf50633_irq_init()
/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Dsh_intc.c153 if (desc->mask_regs) { in sh_intc_locate()
155 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
343 if (desc->mask_regs) { in sh_intc_register_source()
345 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
440 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
449 desc->mask_regs = mask_regs; in sh_intc_init()
475 if (desc->mask_regs) { in sh_intc_init()
477 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Dsh_intc.c137 if (desc->mask_regs) { in sh_intc_locate()
139 struct intc_mask_reg *mr = &desc->mask_regs[i]; in sh_intc_locate()
267 if (desc->mask_regs) { in sh_intc_register_source()
269 struct intc_mask_reg *mr = &desc->mask_regs[i]; in sh_intc_register_source()
385 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
394 desc->mask_regs = mask_regs; in sh_intc_init()
409 if (desc->mask_regs) { in sh_intc_init()
411 struct intc_mask_reg *mr = &desc->mask_regs[i]; in sh_intc_init()
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Dsh_intc.c153 if (desc->mask_regs) { in sh_intc_locate()
155 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
343 if (desc->mask_regs) { in sh_intc_register_source()
345 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
440 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
449 desc->mask_regs = mask_regs; in sh_intc_init()
475 if (desc->mask_regs) { in sh_intc_init()
477 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Dsh_intc.c154 if (desc->mask_regs) { in sh_intc_locate()
156 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
344 if (desc->mask_regs) { in sh_intc_register_source()
346 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
441 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
450 desc->mask_regs = mask_regs; in sh_intc_init()
476 if (desc->mask_regs) { in sh_intc_init()
478 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Dsh_intc.c153 if (desc->mask_regs) { in sh_intc_locate()
155 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
343 if (desc->mask_regs) { in sh_intc_register_source()
345 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
440 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
449 desc->mask_regs = mask_regs; in sh_intc_init()
475 if (desc->mask_regs) { in sh_intc_init()
477 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Dsh_intc.c153 if (desc->mask_regs) { in sh_intc_locate()
155 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
343 if (desc->mask_regs) { in sh_intc_register_source()
345 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
440 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
449 desc->mask_regs = mask_regs; in sh_intc_init()
475 if (desc->mask_regs) { in sh_intc_init()
477 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Dsh_intc.c153 if (desc->mask_regs) { in sh_intc_locate()
155 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
343 if (desc->mask_regs) { in sh_intc_register_source()
345 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
440 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
449 desc->mask_regs = mask_regs; in sh_intc_init()
475 if (desc->mask_regs) { in sh_intc_init()
477 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Dsh_intc.c153 if (desc->mask_regs) { in sh_intc_locate()
155 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
343 if (desc->mask_regs) { in sh_intc_register_source()
345 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
440 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
449 desc->mask_regs = mask_regs; in sh_intc_init()
475 if (desc->mask_regs) { in sh_intc_init()
477 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Dsh_intc.c153 if (desc->mask_regs) { in sh_intc_locate()
155 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_locate()
343 if (desc->mask_regs) { in sh_intc_register_source()
345 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_register_source()
440 struct intc_mask_reg *mask_regs, in sh_intc_init() argument
449 desc->mask_regs = mask_regs; in sh_intc_init()
475 if (desc->mask_regs) { in sh_intc_init()
477 struct intc_mask_reg *mr = desc->mask_regs + i; in sh_intc_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/sh/intc/
H A Dbalancing.c44 struct intc_mask_reg *mr = desc->hw.mask_regs; in intc_dist_data()
49 mr = desc->hw.mask_regs + i; in intc_dist_data()
91 if (!desc->hw.mask_regs) in intc_set_dist_handle()
H A Dcore.c238 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; in register_intc_controller()
259 if (hw->mask_regs) { in register_intc_controller()
261 smp = IS_SMP(hw->mask_regs[i]); in register_intc_controller()
262 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); in register_intc_controller()
263 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); in register_intc_controller()
265 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); in register_intc_controller()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/sh/intc/
H A Dbalancing.c44 struct intc_mask_reg *mr = desc->hw.mask_regs; in intc_dist_data()
49 mr = desc->hw.mask_regs + i; in intc_dist_data()
91 if (!desc->hw.mask_regs) in intc_set_dist_handle()
H A Dcore.c238 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; in register_intc_controller()
259 if (hw->mask_regs) { in register_intc_controller()
261 smp = IS_SMP(hw->mask_regs[i]); in register_intc_controller()
262 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); in register_intc_controller()
263 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); in register_intc_controller()
265 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); in register_intc_controller()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/sh/intc/
H A Dbalancing.c44 struct intc_mask_reg *mr = desc->hw.mask_regs; in intc_dist_data()
49 mr = desc->hw.mask_regs + i; in intc_dist_data()
91 if (!desc->hw.mask_regs) in intc_set_dist_handle()
H A Dcore.c238 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; in register_intc_controller()
259 if (hw->mask_regs) { in register_intc_controller()
261 smp = IS_SMP(hw->mask_regs[i]); in register_intc_controller()
262 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); in register_intc_controller()
263 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); in register_intc_controller()
265 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); in register_intc_controller()
/dports/emulators/qemu/qemu-6.2.0/include/hw/sh4/
H A Dsh_intc.h53 struct intc_mask_reg *mask_regs; member
74 struct intc_mask_reg *mask_regs,
/dports/emulators/qemu42/qemu-4.2.1/include/hw/sh4/
H A Dsh_intc.h53 struct intc_mask_reg *mask_regs; member
74 struct intc_mask_reg *mask_regs,
/dports/emulators/qemu60/qemu-6.0.0/include/hw/sh4/
H A Dsh_intc.h53 struct intc_mask_reg *mask_regs; member
74 struct intc_mask_reg *mask_regs,
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/sh4/
H A Dsh_intc.h54 struct intc_mask_reg *mask_regs; member
75 struct intc_mask_reg *mask_regs,

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