/dports/emulators/qemu-utils/qemu-4.2.1/roms/opensbi/lib/sbi/ |
H A D | sbi_illegal_insn.c | 19 typedef int (*illegal_insn_func)(ulong insn, u32 hartid, ulong mcause, 23 static int truly_illegal_insn(ulong insn, u32 hartid, ulong mcause, in truly_illegal_insn() argument 27 return sbi_trap_redirect(regs, scratch, regs->mepc, mcause, insn); in truly_illegal_insn() 30 static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause, in system_opcode_insn() argument 50 regs->mepc, mcause, insn); in system_opcode_insn() 53 return truly_illegal_insn(insn, hartid, mcause, in system_opcode_insn() 79 return truly_illegal_insn(insn, hartid, mcause, regs, scratch); in system_opcode_insn() 84 return truly_illegal_insn(insn, hartid, mcause, regs, scratch); in system_opcode_insn() 128 int sbi_illegal_insn_handler(u32 hartid, ulong mcause, in sbi_illegal_insn_handler() argument 148 return truly_illegal_insn(insn, hartid, mcause, regs, in sbi_illegal_insn_handler() [all …]
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H A D | sbi_trap.c | 24 ulong mcause, ulong mtval, in sbi_trap_error() argument 29 __func__, hartid, mcause, mtval); in sbi_trap_error() 219 ulong mcause = csr_read(CSR_MCAUSE); in sbi_trap_handler() local 223 if (mcause & (1UL << (__riscv_xlen - 1))) { in sbi_trap_handler() 224 mcause &= ~(1UL << (__riscv_xlen - 1)); in sbi_trap_handler() 225 switch (mcause) { in sbi_trap_handler() 239 switch (mcause) { in sbi_trap_handler() 255 rc = sbi_ecall_handler(hartid, mcause, regs, scratch); in sbi_trap_handler() 266 uptrap->cause = mcause; in sbi_trap_handler() 270 mcause, mtval); in sbi_trap_handler() [all …]
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H A D | sbi_misaligned_ldst.c | 24 int sbi_misaligned_load_handler(u32 hartid, ulong mcause, in sbi_misaligned_load_handler() argument 106 mcause, addr); in sbi_misaligned_load_handler() 131 int sbi_misaligned_store_handler(u32 hartid, ulong mcause, in sbi_misaligned_store_handler() argument 204 mcause, addr); in sbi_misaligned_store_handler()
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/dports/emulators/qemu42/qemu-4.2.1/roms/opensbi/lib/sbi/ |
H A D | sbi_illegal_insn.c | 19 typedef int (*illegal_insn_func)(ulong insn, u32 hartid, ulong mcause, 23 static int truly_illegal_insn(ulong insn, u32 hartid, ulong mcause, in truly_illegal_insn() argument 27 return sbi_trap_redirect(regs, scratch, regs->mepc, mcause, insn); in truly_illegal_insn() 30 static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause, in system_opcode_insn() argument 50 regs->mepc, mcause, insn); in system_opcode_insn() 53 return truly_illegal_insn(insn, hartid, mcause, in system_opcode_insn() 79 return truly_illegal_insn(insn, hartid, mcause, regs, scratch); in system_opcode_insn() 84 return truly_illegal_insn(insn, hartid, mcause, regs, scratch); in system_opcode_insn() 128 int sbi_illegal_insn_handler(u32 hartid, ulong mcause, in sbi_illegal_insn_handler() argument 148 return truly_illegal_insn(insn, hartid, mcause, regs, in sbi_illegal_insn_handler() [all …]
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H A D | sbi_trap.c | 24 ulong mcause, ulong mtval, in sbi_trap_error() argument 29 __func__, hartid, mcause, mtval); in sbi_trap_error() 219 ulong mcause = csr_read(CSR_MCAUSE); in sbi_trap_handler() local 223 if (mcause & (1UL << (__riscv_xlen - 1))) { in sbi_trap_handler() 224 mcause &= ~(1UL << (__riscv_xlen - 1)); in sbi_trap_handler() 225 switch (mcause) { in sbi_trap_handler() 239 switch (mcause) { in sbi_trap_handler() 255 rc = sbi_ecall_handler(hartid, mcause, regs, scratch); in sbi_trap_handler() 266 uptrap->cause = mcause; in sbi_trap_handler() 270 mcause, mtval); in sbi_trap_handler() [all …]
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H A D | sbi_misaligned_ldst.c | 24 int sbi_misaligned_load_handler(u32 hartid, ulong mcause, in sbi_misaligned_load_handler() argument 106 mcause, addr); in sbi_misaligned_load_handler() 131 int sbi_misaligned_store_handler(u32 hartid, ulong mcause, in sbi_misaligned_store_handler() argument 204 mcause, addr); in sbi_misaligned_store_handler()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/opensbi/lib/sbi/ |
H A D | sbi_illegal_insn.c | 19 typedef int (*illegal_insn_func)(ulong insn, u32 hartid, ulong mcause, 23 static int truly_illegal_insn(ulong insn, u32 hartid, ulong mcause, in truly_illegal_insn() argument 30 trap.cause = mcause; in truly_illegal_insn() 38 static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause, in system_opcode_insn() argument 57 return truly_illegal_insn(insn, hartid, mcause, in system_opcode_insn() 61 return truly_illegal_insn(insn, hartid, mcause, in system_opcode_insn() 87 return truly_illegal_insn(insn, hartid, mcause, regs, scratch); in system_opcode_insn() 92 return truly_illegal_insn(insn, hartid, mcause, regs, scratch); in system_opcode_insn() 136 int sbi_illegal_insn_handler(u32 hartid, ulong mcause, ulong insn, in sbi_illegal_insn_handler() argument 152 return truly_illegal_insn(insn, hartid, mcause, regs, in sbi_illegal_insn_handler() [all …]
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H A D | sbi_trap.c | 23 ulong mcause, ulong mtval, ulong mtval2, in sbi_trap_error() argument 28 __func__, hartid, mcause, mtval); in sbi_trap_error() 221 ulong mcause = csr_read(CSR_MCAUSE); in sbi_trap_handler() local 230 if (mcause & (1UL << (__riscv_xlen - 1))) { in sbi_trap_handler() 231 mcause &= ~(1UL << (__riscv_xlen - 1)); in sbi_trap_handler() 232 switch (mcause) { in sbi_trap_handler() 246 switch (mcause) { in sbi_trap_handler() 278 uptrap->cause = mcause; in sbi_trap_handler() 284 trap.cause = mcause; in sbi_trap_handler() 295 trap.cause = mcause; in sbi_trap_handler() [all …]
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H A D | sbi_misaligned_ldst.c | 24 int sbi_misaligned_load_handler(u32 hartid, ulong mcause, in sbi_misaligned_load_handler() argument 115 uptrap.cause = mcause; in sbi_misaligned_load_handler() 146 int sbi_misaligned_store_handler(u32 hartid, ulong mcause, in sbi_misaligned_store_handler() argument 228 uptrap.cause = mcause; in sbi_misaligned_store_handler()
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H A D | sbi_ecall.c | 74 int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs, in sbi_ecall_handler() argument
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/dports/emulators/qemu5/qemu-5.2.0/roms/opensbi/lib/sbi/ |
H A D | sbi_trap.c | 23 ulong mcause, ulong mtval, ulong mtval2, in sbi_trap_error() argument 30 __func__, hartid, mcause, mtval); in sbi_trap_error() 216 ulong mcause = csr_read(CSR_MCAUSE); in sbi_trap_handler() local 225 if (mcause & (1UL << (__riscv_xlen - 1))) { in sbi_trap_handler() 226 mcause &= ~(1UL << (__riscv_xlen - 1)); in sbi_trap_handler() 227 switch (mcause) { in sbi_trap_handler() 241 switch (mcause) { in sbi_trap_handler() 262 trap.cause = mcause; in sbi_trap_handler() 272 sbi_trap_error(msg, rc, mcause, mtval, mtval2, mtinst, regs); in sbi_trap_handler()
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/dports/emulators/qemu60/qemu-6.0.0/roms/opensbi/lib/sbi/ |
H A D | sbi_trap.c | 24 ulong mcause, ulong mtval, ulong mtval2, in sbi_trap_error() argument 31 __func__, hartid, mcause, mtval); in sbi_trap_error() 217 ulong mcause = csr_read(CSR_MCAUSE); in sbi_trap_handler() local 226 if (mcause & (1UL << (__riscv_xlen - 1))) { in sbi_trap_handler() 227 mcause &= ~(1UL << (__riscv_xlen - 1)); in sbi_trap_handler() 228 switch (mcause) { in sbi_trap_handler() 242 switch (mcause) { in sbi_trap_handler() 263 trap.cause = mcause; in sbi_trap_handler() 273 sbi_trap_error(msg, rc, mcause, mtval, mtval2, mtinst, regs); in sbi_trap_handler()
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/dports/sysutils/opensbi/opensbi-0.9/lib/sbi/ |
H A D | sbi_trap.c | 24 ulong mcause, ulong mtval, ulong mtval2, in sbi_trap_error() argument 31 __func__, hartid, mcause, mtval); in sbi_trap_error() 217 ulong mcause = csr_read(CSR_MCAUSE); in sbi_trap_handler() local 226 if (mcause & (1UL << (__riscv_xlen - 1))) { in sbi_trap_handler() 227 mcause &= ~(1UL << (__riscv_xlen - 1)); in sbi_trap_handler() 228 switch (mcause) { in sbi_trap_handler() 242 switch (mcause) { in sbi_trap_handler() 263 trap.cause = mcause; in sbi_trap_handler() 273 sbi_trap_error(msg, rc, mcause, mtval, mtval2, mtinst, regs); in sbi_trap_handler()
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/dports/emulators/qemu/qemu-6.2.0/roms/opensbi/lib/sbi/ |
H A D | sbi_trap.c | 24 ulong mcause, ulong mtval, ulong mtval2, in sbi_trap_error() argument 31 __func__, hartid, mcause, mtval); in sbi_trap_error() 217 ulong mcause = csr_read(CSR_MCAUSE); in sbi_trap_handler() local 226 if (mcause & (1UL << (__riscv_xlen - 1))) { in sbi_trap_handler() 227 mcause &= ~(1UL << (__riscv_xlen - 1)); in sbi_trap_handler() 228 switch (mcause) { in sbi_trap_handler() 242 switch (mcause) { in sbi_trap_handler() 263 trap.cause = mcause; in sbi_trap_handler() 273 sbi_trap_error(msg, rc, mcause, mtval, mtval2, mtinst, regs); in sbi_trap_handler()
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/dports/emulators/qemu42/qemu-4.2.1/roms/opensbi/include/sbi/ |
H A D | sbi_misaligned_ldst.h | 18 int sbi_misaligned_load_handler(u32 hartid, ulong mcause, 22 int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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H A D | sbi_illegal_insn.h | 18 int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
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H A D | sbi_ecall.h | 22 int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/opensbi/include/sbi/ |
H A D | sbi_misaligned_ldst.h | 18 int sbi_misaligned_load_handler(u32 hartid, ulong mcause, 22 int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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H A D | sbi_illegal_insn.h | 18 int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
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H A D | sbi_ecall.h | 22 int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/opensbi/include/sbi/ |
H A D | sbi_misaligned_ldst.h | 18 int sbi_misaligned_load_handler(u32 hartid, ulong mcause, 23 int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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H A D | sbi_illegal_insn.h | 18 int sbi_illegal_insn_handler(u32 hartid, ulong mcause, ulong insn,
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H A D | sbi_ecall.h | 53 int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
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/dports/print/lilypond/lilypond-2.22.1/lily/ |
H A D | accidental-placement.cc | 43 Stream_event *mcause = acc->get_y_parent ()->event_cause (); in accidental_pitch() local 45 if (!mcause) in accidental_pitch() 51 return unsmob<Pitch> (get_property (mcause, "pitch")); in accidental_pitch()
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/dports/print/lilypond-devel/lilypond-2.23.5/lily/ |
H A D | accidental-placement.cc | 45 Stream_event *mcause = acc->get_y_parent ()->event_cause (); in accidental_pitch() local 47 if (!mcause) in accidental_pitch() 53 return unsmob<Pitch> (get_property (mcause, "pitch")); in accidental_pitch()
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