Searched refs:miso_pad_i (Results 1 – 7 of 7) sorted by relevance
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wb_spi/rtl/verilog/ |
H A D | spi_top.v | 56 ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i 77 input miso_pad_i; // master in slave out port 287 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
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H A D | spi_top16.v | 60 output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); port 182 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/spi/rtl/verilog/ |
H A D | spi_top.v | 54 ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i 75 input miso_pad_i; // master in slave out port 285 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
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H A D | spi_top16.v | 58 output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); port 180 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wb_spi/bench/verilog/ |
H A D | tb_spi_top.v | 100 .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/spi/bench/verilog/ |
H A D | tb_spi_top.v | 100 .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/top/N2x0/ |
H A D | u2plus_core.v | 612 .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );
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