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Searched refs:miso_pad_i (Results 1 – 7 of 7) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wb_spi/rtl/verilog/
H A Dspi_top.v56 ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
77 input miso_pad_i; // master in slave out port
287 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
H A Dspi_top16.v60 output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); port
182 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/spi/rtl/verilog/
H A Dspi_top.v54 ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
75 input miso_pad_i; // master in slave out port
285 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
H A Dspi_top16.v58 output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); port
180 .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wb_spi/bench/verilog/
H A Dtb_spi_top.v100 .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/spi/bench/verilog/
H A Dtb_spi_top.v100 .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/top/N2x0/
H A Du2plus_core.v612 .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );