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Searched refs:mmCP_DFY_ADDR_LO (Results 1 – 25 of 25) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu7_smumgr.c514 cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo); in execute_pwr_dfy_table()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu7_smumgr.c514 cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo); in execute_pwr_dfy_table()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu7_smumgr.c514 cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo); in execute_pwr_dfy_table()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h178 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_7_0_d.h178 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_8_0_d.h200 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_8_1_d.h200 #define mmCP_DFY_ADDR_LO 0x3023 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h178 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_7_0_d.h178 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_8_1_d.h200 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_8_0_d.h200 #define mmCP_DFY_ADDR_LO 0x3023 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h178 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_7_2_d.h178 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_8_0_d.h200 #define mmCP_DFY_ADDR_LO 0x3023 macro
H A Dgfx_8_1_d.h200 #define mmCP_DFY_ADDR_LO 0x3023 macro
/dports/sysutils/roct/ROCT-Thunk-Interface-9d1fb76/tests/kfdtest/include/asic_reg/
H A Dgfx_7_2_d.h178 #define mmCP_DFY_ADDR_LO 0x3023 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2304 #define mmCP_DFY_ADDR_LO macro
H A Dgc_9_1_offset.h2581 #define mmCP_DFY_ADDR_LO macro
H A Dgc_9_2_1_offset.h2519 #define mmCP_DFY_ADDR_LO macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2304 #define mmCP_DFY_ADDR_LO macro
H A Dgc_9_2_1_offset.h2519 #define mmCP_DFY_ADDR_LO macro
H A Dgc_9_1_offset.h2581 #define mmCP_DFY_ADDR_LO macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2304 #define mmCP_DFY_ADDR_LO macro
H A Dgc_9_1_offset.h2581 #define mmCP_DFY_ADDR_LO macro
H A Dgc_9_2_1_offset.h2519 #define mmCP_DFY_ADDR_LO macro