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Searched refs:mmCP_DFY_CNTL (Results 1 – 25 of 28) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/inc/
H A Dpolaris10_pwrvirus.h53 { 0x80000004, mmCP_DFY_CNTL },
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/inc/
H A Dpolaris10_pwrvirus.h53 { 0x80000004, mmCP_DFY_CNTL },
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/inc/
H A Dpolaris10_pwrvirus.h53 { 0x80000004, mmCP_DFY_CNTL },
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu7_smumgr.c512 cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl); in execute_pwr_dfy_table()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu7_smumgr.c512 cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl); in execute_pwr_dfy_table()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu7_smumgr.c512 cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl); in execute_pwr_dfy_table()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_7_0_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_8_0_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_8_1_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_7_0_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_8_1_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_8_0_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_7_2_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_8_0_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
H A Dgfx_8_1_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
/dports/sysutils/roct/ROCT-Thunk-Interface-9d1fb76/tests/kfdtest/include/asic_reg/
H A Dgfx_7_2_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2298 #define mmCP_DFY_CNTL macro
H A Dgc_9_1_offset.h2575 #define mmCP_DFY_CNTL macro
H A Dgc_9_2_1_offset.h2513 #define mmCP_DFY_CNTL macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2298 #define mmCP_DFY_CNTL macro
H A Dgc_9_2_1_offset.h2513 #define mmCP_DFY_CNTL macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2298 #define mmCP_DFY_CNTL macro

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