| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_d.h | 501 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_7_2_d.h | 203 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_7_0_d.h | 203 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_8_1_d.h | 228 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_8_0_d.h | 227 #define mmCP_RB1_CNTL 0x3061 macro
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_d.h | 501 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_7_2_d.h | 203 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_7_0_d.h | 203 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_8_0_d.h | 227 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_8_1_d.h | 228 #define mmCP_RB1_CNTL 0x3061 macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_d.h | 501 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_7_0_d.h | 203 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_7_2_d.h | 203 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_8_0_d.h | 227 #define mmCP_RB1_CNTL 0x3061 macro
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| H A D | gfx_8_1_d.h | 228 #define mmCP_RB1_CNTL 0x3061 macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v6_0.c | 2200 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
2202 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
2211 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v6_0.c | 2200 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
2202 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
2211 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v6_0.c | 2200 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
2202 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
2211 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
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| /dports/sysutils/roct/ROCT-Thunk-Interface-9d1fb76/tests/kfdtest/include/asic_reg/ |
| H A D | gfx_7_2_d.h | 203 #define mmCP_RB1_CNTL 0x3061 macro
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2450 #define mmCP_RB1_CNTL … macro
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| H A D | gc_9_1_offset.h | 2727 #define mmCP_RB1_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 2665 #define mmCP_RB1_CNTL … macro
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2450 #define mmCP_RB1_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 2665 #define mmCP_RB1_CNTL … macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2450 #define mmCP_RB1_CNTL … macro
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