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Searched refs:mmMAILBOX_CONTROL (Results 1 – 18 of 18) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c323 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
325 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
328 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
337 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
345 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
348 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
372 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
393 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
403 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
H A Dmxgpu_nv.h63 #define mmMAILBOX_CONTROL 0xE5E macro
65 #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c323 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
325 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
328 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
337 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
345 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
348 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
372 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
393 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
403 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
H A Dmxgpu_nv.h63 #define mmMAILBOX_CONTROL 0xE5E macro
65 #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c323 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
325 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
328 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
337 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
345 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
348 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
372 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
393 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
403 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
H A Dmxgpu_nv.h63 #define mmMAILBOX_CONTROL 0xE5E macro
65 #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_d.h186 #define mmMAILBOX_CONTROL 0x14d0 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_d.h186 #define mmMAILBOX_CONTROL 0x14d0 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_d.h186 #define mmMAILBOX_CONTROL 0x14d0 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1149 #define mmMAILBOX_CONTROL … macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1149 #define mmMAILBOX_CONTROL … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1149 #define mmMAILBOX_CONTROL … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h4502 #define mmMAILBOX_CONTROL … macro
H A Dnbio_7_4_offset.h2932 #define mmMAILBOX_CONTROL … macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h4502 #define mmMAILBOX_CONTROL … macro
H A Dnbio_7_4_offset.h2932 #define mmMAILBOX_CONTROL … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h4502 #define mmMAILBOX_CONTROL … macro
H A Dnbio_7_4_offset.h2932 #define mmMAILBOX_CONTROL … macro