Searched refs:mmMP1_SMN_IH_SW_INT (Results 1 – 18 of 18) sorted by relevance
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| H A D | mp_10_0_offset.h | 328 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_12_0_0_offset.h | 328 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_9_0_offset.h | 342 #define mmMP1_SMN_IH_SW_INT 0x02c2 macro
|
| H A D | mp_11_0_offset.h | 332 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_11_5_0_offset.h | 376 #define mmMP1_SMN_IH_SW_INT … macro
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| H A D | mp_10_0_offset.h | 328 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_12_0_0_offset.h | 328 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_11_0_offset.h | 332 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_9_0_offset.h | 342 #define mmMP1_SMN_IH_SW_INT 0x02c2 macro
|
| H A D | mp_11_5_0_offset.h | 376 #define mmMP1_SMN_IH_SW_INT … macro
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| H A D | mp_12_0_0_offset.h | 328 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_10_0_offset.h | 328 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_11_0_offset.h | 332 #define mmMP1_SMN_IH_SW_INT … macro
|
| H A D | mp_9_0_offset.h | 342 #define mmMP1_SMN_IH_SW_INT 0x02c2 macro
|
| H A D | mp_11_5_0_offset.h | 376 #define mmMP1_SMN_IH_SW_INT … macro
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | smu_v11_0.c | 1293 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); in smu_v11_0_set_irq_state()
1296 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); in smu_v11_0_set_irq_state()
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | smu_v11_0.c | 1293 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); in smu_v11_0_set_irq_state()
1296 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); in smu_v11_0_set_irq_state()
|
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | smu_v11_0.c | 1293 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); in smu_v11_0_set_irq_state()
1296 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); in smu_v11_0_set_irq_state()
|