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Searched refs:mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX (Results 1 – 15 of 15) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6034 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_9_1_offset.h6256 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_9_2_1_offset.h6232 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_10_1_0_offset.h9354 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_10_3_0_offset.h9184 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6034 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_9_2_1_offset.h6232 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_9_1_offset.h6256 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_10_1_0_offset.h9354 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_10_3_0_offset.h9184 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6034 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_9_1_offset.h6256 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_9_2_1_offset.h6232 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_10_1_0_offset.h9354 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro
H A Dgc_10_3_0_offset.h9184 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … macro