| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 216 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_0_offset.h | 4644 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_1_offset.h | 4874 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_2_1_offset.h | 4830 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_10_1_0_offset.h | 7108 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_10_3_0_offset.h | 6733 #define mmSCRATCH_REG1_BASE_IDX … macro
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 216 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_0_offset.h | 4644 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_2_1_offset.h | 4830 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_1_offset.h | 4874 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_10_1_0_offset.h | 7108 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_10_3_0_offset.h | 6733 #define mmSCRATCH_REG1_BASE_IDX … macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 216 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_0_offset.h | 4644 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_1_offset.h | 4874 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_9_2_1_offset.h | 4830 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_10_1_0_offset.h | 7108 #define mmSCRATCH_REG1_BASE_IDX … macro
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| H A D | gc_10_3_0_offset.h | 6733 #define mmSCRATCH_REG1_BASE_IDX … macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 748 …scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
749 …scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
750 …scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
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| H A D | gfx_v10_0.c | 1476 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; in gfx_v10_rlcg_rw()
1480 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; in gfx_v10_rlcg_rw()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 748 …scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
749 …scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
750 …scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
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| H A D | gfx_v10_0.c | 1476 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; in gfx_v10_rlcg_rw()
1480 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; in gfx_v10_rlcg_rw()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 748 …scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
749 …scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
750 …scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_rw()
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| H A D | gfx_v10_0.c | 1476 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; in gfx_v10_rlcg_rw()
1480 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; in gfx_v10_rlcg_rw()
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