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Searched refs:mmUVD_CGC_GATE (Results 1 – 25 of 60) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_4_0_d.h35 #define mmUVD_CGC_GATE 0x3D2A macro
H A Duvd_3_1_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_5_0_d.h48 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_6_0_d.h64 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_7_0_offset.h144 #define mmUVD_CGC_GATE … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_4_0_d.h35 #define mmUVD_CGC_GATE 0x3D2A macro
H A Duvd_3_1_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_5_0_d.h48 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_6_0_d.h64 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_7_0_offset.h144 #define mmUVD_CGC_GATE … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h35 #define mmUVD_CGC_GATE 0x3D2A macro
H A Duvd_4_2_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_3_1_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_5_0_d.h48 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_6_0_d.h64 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_7_0_offset.h144 #define mmUVD_CGC_GATE … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c609 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
647 WREG32(mmUVD_CGC_GATE, data3); in uvd_v5_0_enable_clock_gating()
702 data = RREG32(mmUVD_CGC_GATE);
733 WREG32(mmUVD_CGC_GATE, data);
H A Duvd_v6_0.c622 data = RREG32(mmUVD_CGC_GATE);
690 WREG32(mmUVD_CGC_GATE, data);
1264 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1311 WREG32(mmUVD_CGC_GATE, data3); in uvd_v6_0_enable_clock_gating()
1367 data = RREG32(mmUVD_CGC_GATE);
1400 WREG32(mmUVD_CGC_GATE, data);
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c609 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
647 WREG32(mmUVD_CGC_GATE, data3); in uvd_v5_0_enable_clock_gating()
702 data = RREG32(mmUVD_CGC_GATE);
733 WREG32(mmUVD_CGC_GATE, data);
H A Duvd_v6_0.c622 data = RREG32(mmUVD_CGC_GATE);
690 WREG32(mmUVD_CGC_GATE, data);
1264 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1311 WREG32(mmUVD_CGC_GATE, data3); in uvd_v6_0_enable_clock_gating()
1367 data = RREG32(mmUVD_CGC_GATE);
1400 WREG32(mmUVD_CGC_GATE, data);
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c609 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
647 WREG32(mmUVD_CGC_GATE, data3); in uvd_v5_0_enable_clock_gating()
702 data = RREG32(mmUVD_CGC_GATE);
733 WREG32(mmUVD_CGC_GATE, data);
H A Duvd_v6_0.c622 data = RREG32(mmUVD_CGC_GATE);
690 WREG32(mmUVD_CGC_GATE, data);
1264 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1311 WREG32(mmUVD_CGC_GATE, data3); in uvd_v6_0_enable_clock_gating()
1367 data = RREG32(mmUVD_CGC_GATE);
1400 WREG32(mmUVD_CGC_GATE, data);
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h304 #define mmUVD_CGC_GATE … macro

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