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Searched refs:mmUVD_CONTEXT_ID (Results 1 – 25 of 48) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
146 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v3_1_ring_test_ring()
151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_test_ring()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
H A Duvd_v4_2.c451 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence()
482 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v4_2_ring_test_ring()
487 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_test_ring()
491 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v4_2_ring_test_ring()
H A Duvd_v5_0.c468 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence()
499 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v5_0_ring_test_ring()
503 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_test_ring()
507 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
146 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v3_1_ring_test_ring()
151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_test_ring()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
H A Duvd_v4_2.c451 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence()
482 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v4_2_ring_test_ring()
487 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_test_ring()
491 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v4_2_ring_test_ring()
H A Duvd_v5_0.c468 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence()
499 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v5_0_ring_test_ring()
503 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_test_ring()
507 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c451 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence()
482 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v4_2_ring_test_ring()
487 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_test_ring()
491 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v4_2_ring_test_ring()
H A Duvd_v3_1.c115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
146 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v3_1_ring_test_ring()
151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_test_ring()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
H A Duvd_v5_0.c468 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence()
499 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v5_0_ring_test_ring()
503 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_test_ring()
507 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h81 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_4_0_d.h38 #define mmUVD_CONTEXT_ID 0x3DBD macro
H A Duvd_3_1_d.h83 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_5_0_d.h87 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_6_0_d.h103 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_7_0_offset.h218 #define mmUVD_CONTEXT_ID … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h81 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_4_0_d.h38 #define mmUVD_CONTEXT_ID 0x3DBD macro
H A Duvd_3_1_d.h83 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_5_0_d.h87 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_6_0_d.h103 #define mmUVD_CONTEXT_ID 0x3dbd macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h38 #define mmUVD_CONTEXT_ID 0x3DBD macro
H A Duvd_4_2_d.h81 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_3_1_d.h83 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_5_0_d.h87 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_6_0_d.h103 #define mmUVD_CONTEXT_ID 0x3dbd macro

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