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Searched refs:mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH (Results 1 – 15 of 15) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h272 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_2_5_offset.h271 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_2_0_0_offset.h256 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_3_0_0_offset.h499 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h272 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_2_5_offset.h271 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_2_0_0_offset.h256 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_3_0_0_offset.h499 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h272 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_2_5_offset.h271 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_2_0_0_offset.h256 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
H A Dvcn_3_0_0_offset.h499 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c239 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c239 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c239 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()