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Searched refs:mmUVD_SUVD_CGC_GATE (Results 1 – 25 of 42) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c608 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
646 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
703 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
734 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Duvd_v6_0.c623 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
691 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1263 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1310 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v6_0_enable_clock_gating()
1368 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1401 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Duvd_v7_0.c1594 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1641 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1650 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1683 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
H A Dvcn_v1_0.c514 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
539 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
675 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c608 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
646 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
703 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
734 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Duvd_v6_0.c623 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
691 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1263 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1310 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v6_0_enable_clock_gating()
1368 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1401 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Duvd_v7_0.c1594 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1641 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1650 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1683 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c608 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
646 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
703 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
734 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Duvd_v6_0.c623 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
691 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1263 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1310 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v6_0_enable_clock_gating()
1368 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1401 WREG32(mmUVD_SUVD_CGC_GATE, data1);
H A Duvd_v7_0.c1594 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1641 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1650 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1683 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_d.h89 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_6_0_d.h105 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_7_0_offset.h66 #define mmUVD_SUVD_CGC_GATE … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_d.h89 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_6_0_d.h105 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_7_0_offset.h66 #define mmUVD_SUVD_CGC_GATE … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_d.h89 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_6_0_d.h105 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
H A Duvd_7_0_offset.h66 #define mmUVD_SUVD_CGC_GATE … macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h154 #define mmUVD_SUVD_CGC_GATE … macro
H A Dvcn_2_5_offset.h505 #define mmUVD_SUVD_CGC_GATE … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h154 #define mmUVD_SUVD_CGC_GATE … macro
H A Dvcn_2_5_offset.h505 #define mmUVD_SUVD_CGC_GATE … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h154 #define mmUVD_SUVD_CGC_GATE … macro
H A Dvcn_2_5_offset.h505 #define mmUVD_SUVD_CGC_GATE … macro

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