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/dports/www/chromium-legacy/chromium-88.0.4324.182/ash/system/palette/
H A Dpalette_tool_manager_unittest.cc97 TestTool* mode_1 = BuildTool(PaletteGroup::MODE, PaletteToolId::MAGNIFY); in TEST_F() local
106 palette_tool_manager_->ActivateTool(mode_1->GetToolId()); in TEST_F()
109 EXPECT_TRUE(mode_1->enabled()); in TEST_F()
117 EXPECT_TRUE(mode_1->enabled()); in TEST_F()
122 EXPECT_TRUE(mode_1->enabled()); in TEST_F()
/dports/science/getdp/getdp-3.4.0-source/contrib/pewe/fortran/
H A Dmain_surface_wave_convex.f906 integer, parameter :: mode_1 = 1 variable
23 bi = B_imag_arr(mode_1,mode_2)
24 c = omega_arr(mode_1,mode_2)/dble(n)
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/fosphor/
H A Df15_rise_decay.v32 reg mode_1; register
52 mode_1 <= mode_0;
59 if (mode_1)
/dports/graphics/aloadimage/arcan-0.6.1/tests/interactive/outputs/
H A Doutputs.lua12 local function mode_1(set) function
57 local modes = {mode_1, mode_2, mode_3, mode_4, mode_5};
/dports/sysutils/acfgfs/arcan-0.6.1/tests/interactive/outputs/
H A Doutputs.lua12 local function mode_1(set) function
57 local modes = {mode_1, mode_2, mode_3, mode_4, mode_5};
/dports/x11/aclip/arcan-0.6.1/tests/interactive/outputs/
H A Doutputs.lua12 local function mode_1(set) function
57 local modes = {mode_1, mode_2, mode_3, mode_4, mode_5};
/dports/x11/arcan-trayicon/arcan-0.6.1/tests/interactive/outputs/
H A Doutputs.lua12 local function mode_1(set) function
57 local modes = {mode_1, mode_2, mode_3, mode_4, mode_5};
/dports/devel/z88dk/z88dk/include/
H A Dmsx.h38 mode_1 = 0x6F, // INIT32 enumerator
48 mode_1 = 0, // patched code for INIT32 enumerator
58 mode_1 = 0, // patched code for INIT32 enumerator
67 mode_1 = 1, enumerator
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-octeon/
H A Docteon_qlm.c2676 .mode_1.s = { .pll_16p5en = 0x0,
2695 .mode_1.s = { .pll_16p5en = 0x0,
2714 .mode_1.s = { .pll_16p5en = 0x0,
2781 .mode_1.s = { .pll_16p5en = 0x1,
2800 .mode_1.s = { .pll_16p5en = 0x1,
3572 cvmx_gserx_pll_px_mode_1_t mode_1; in __qlm_setup_pll_cn78xx() local
3599 mode_1.s.pll_16p5en = clk_settings->mode_1.s.pll_16p5en; in __qlm_setup_pll_cn78xx()
3600 mode_1.s.pll_cpadj = clk_settings->mode_1.s.pll_cpadj; in __qlm_setup_pll_cn78xx()
3601 mode_1.s.pll_pcie3en = clk_settings->mode_1.s.pll_pcie3en; in __qlm_setup_pll_cn78xx()
3602 mode_1.s.pll_opr = clk_settings->mode_1.s.pll_opr; in __qlm_setup_pll_cn78xx()
[all …]

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