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Searched refs:msr0 (Results 1 – 25 of 393) sorted by relevance

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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/sim/frv/
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
/dports/devel/avr-gdb/gdb-7.3.1/sim/testsuite/sim/frv/
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
/dports/devel/gdb761/gdb-7.6.1/sim/testsuite/sim/frv/
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/sim/frv/
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 74 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/sim/frv/fr550/
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
/dports/devel/avr-gdb/gdb-7.3.1/sim/testsuite/sim/frv/fr550/
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmsubhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 53 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 54 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set [all …]`
/dports/devel/gdb761/gdb-7.6.1/sim/testsuite/sim/frv/fr550/
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/testsuite/sim/frv/fr550/
H A D	cmaddhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmsubhss.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 73 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 83 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`
H A D	cmaddhus.cgs	`16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 54 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 62 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 63 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 2,1,1,msr0 ; msr0.ovf set [all …]`

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