/dports/emulators/qemu5/qemu-5.2.0/target/ppc/ |
H A D | helper_regs.h | 82 env->immu_idx += msr_ir ? 0 : 2; in hreg_compute_mem_idx() 135 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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H A D | mmu-hash64.c | 743 if (msr_ir) { in ppc_hash64_set_isi() 892 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { in ppc_hash64_handle_mmu_fault()
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H A D | mmu_helper.c | 499 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, in get_segment_6xx_tlb() 798 if (msr_ir != (tlb->attr & 1)) { in mmubooke_check_tlb() 1049 if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { in mmubooke206_check_tlb() 1421 bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) in get_physical_address_wtlb() 1534 as = msr_ir; in booke206_update_mas_tlb_miss()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/ppc/ |
H A D | helper_regs.h | 82 env->immu_idx += msr_ir ? 0 : 2; in hreg_compute_mem_idx() 135 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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H A D | mmu-radix64.c | 234 (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0)))) { in ppc_radix64_handle_mmu_fault()
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H A D | mmu-hash64.c | 743 if (msr_ir) { in ppc_hash64_set_isi() 892 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { in ppc_hash64_handle_mmu_fault()
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H A D | mmu_helper.c | 499 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, in get_segment_6xx_tlb() 798 if (msr_ir != (tlb->attr & 1)) { in mmubooke_check_tlb() 1049 if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { in mmubooke206_check_tlb() 1421 bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) in get_physical_address_wtlb() 1534 as = msr_ir; in booke206_update_mas_tlb_miss()
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/dports/emulators/qemu42/qemu-4.2.1/target/ppc/ |
H A D | helper_regs.h | 81 env->immu_idx += msr_ir ? 0 : 2; in hreg_compute_mem_idx() 130 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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H A D | mmu-radix64.c | 234 (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0)))) { in ppc_radix64_handle_mmu_fault()
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H A D | mmu_helper.c | 499 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, in get_segment_6xx_tlb() 798 if (msr_ir != (tlb->attr & 1)) { in mmubooke_check_tlb() 1049 if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { in mmubooke206_check_tlb() 1421 bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) in get_physical_address_wtlb() 1534 as = msr_ir; in booke206_update_mas_tlb_miss()
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/dports/emulators/qemu-utils/qemu-4.2.1/target/ppc/ |
H A D | helper_regs.h | 81 env->immu_idx += msr_ir ? 0 : 2; in hreg_compute_mem_idx() 130 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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H A D | mmu-radix64.c | 234 (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0)))) { in ppc_radix64_handle_mmu_fault()
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H A D | mmu_helper.c | 499 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, in get_segment_6xx_tlb() 798 if (msr_ir != (tlb->attr & 1)) { in mmubooke_check_tlb() 1049 if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { in mmubooke206_check_tlb() 1421 bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) in get_physical_address_wtlb() 1534 as = msr_ir; in booke206_update_mas_tlb_miss()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/ppc/ |
H A D | helper_regs.h | 80 env->immu_idx += msr_ir ? 0 : 2; in hreg_compute_mem_idx() 129 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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H A D | mmu-radix64.c | 270 (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0)))) { in ppc_radix64_handle_mmu_fault()
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H A D | mmu_helper.c | 493 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, in get_segment_6xx_tlb() 788 if (msr_ir != (tlb->attr & 1)) { in mmubooke_check_tlb() 1038 if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { in mmubooke206_check_tlb() 1415 bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) in get_physical_address_wtlb() 1526 as = msr_ir; in booke206_update_mas_tlb_miss()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/ppc/ |
H A D | helper_regs.h | 82 env->immu_idx += msr_ir ? 0 : 2; in hreg_compute_mem_idx() 135 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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H A D | mmu-radix64.c | 234 (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0)))) { in ppc_radix64_handle_mmu_fault()
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H A D | mmu-hash64.c | 692 if (msr_ir) { in ppc_hash64_set_isi() 841 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { in ppc_hash64_handle_mmu_fault()
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/dports/emulators/qemu60/qemu-6.0.0/target/ppc/ |
H A D | helper_regs.h | 82 env->immu_idx += msr_ir ? 0 : 2; in hreg_compute_mem_idx() 135 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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H A D | mmu-hash64.c | 743 if (msr_ir) { in ppc_hash64_set_isi() 892 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { in ppc_hash64_handle_mmu_fault()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/ppc/ |
H A D | mmu_common.c | 407 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, in get_segment_6xx_tlb() 661 if ((access_type == MMU_INST_FETCH ? msr_ir : msr_dr) != (tlb->attr & 1)) { in mmubooke_check_tlb() 872 as = msr_ir; in mmubooke206_check_tlb() 1232 bool real_mode = (type == ACCESS_CODE && msr_ir == 0) in get_physical_address_wtlb() 1296 as = msr_ir; in booke206_update_mas_tlb_miss()
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H A D | helper_regs.c | 216 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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/dports/emulators/qemu/qemu-6.2.0/target/ppc/ |
H A D | mmu_common.c | 407 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, in get_segment_6xx_tlb() 661 if ((access_type == MMU_INST_FETCH ? msr_ir : msr_dr) != (tlb->attr & 1)) { in mmubooke_check_tlb() 872 as = msr_ir; in mmubooke206_check_tlb() 1232 bool real_mode = (type == ACCESS_CODE && msr_ir == 0) in get_physical_address_wtlb() 1296 as = msr_ir; in booke206_update_mas_tlb_miss()
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H A D | helper_regs.c | 225 if (((value >> MSR_IR) & 1) != msr_ir || in hreg_store_msr()
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