Searched refs:muxcy (Results 1 – 6 of 6) sorted by relevance
| /dports/cad/iverilog/verilog-11.0/tgt-fpga/ |
| H A D | d-virtex.c | 101 edif_add_to_joint(jnt, muxcy, MUXCY_S); in virtex_or_wide()
121 edif_add_to_joint(jnt, muxcy, MUXCY_CI); in virtex_or_wide()
125 edif_add_to_joint(jnt, muxcy, MUXCY_CI); in virtex_or_wide()
129 muxcy_down = muxcy; in virtex_or_wide()
599 edif_cellref_t muxcy; in virtex_ge() local
620 muxcy_prev = muxcy; in virtex_ge()
784 edif_cellref_t muxcy0 = muxcy; in virtex_add()
796 muxcy = 0; in virtex_add()
801 if (muxcy) edif_add_to_joint(jnt, muxcy, MUXCY_CI); in virtex_add()
808 if (muxcy) edif_add_to_joint(jnt, muxcy, MUXCY_S); in virtex_add()
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/ticket32/ |
| H A D | muxcy.vhdl | 4 entity muxcy is entity
7 end muxcy;
9 architecture behav of muxcy is
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| H A D | testsuite.sh | 10 analyze --work=unisim muxcy.vhdl
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/ |
| H A D | arith_map.v | 46 MUXCY muxcy ( instance
141 MUXCY muxcy ( instance
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| /dports/lang/pocl/pocl-1.8/examples/accel/rtl/simulation/vhdl/ |
| H A D | generic_sru_sim.vhd | 88 -- muxcy xilinx primitive component (carry chain multiplexer) --
89 component muxcy
284 -- simple incrementer, using dedicated hardware (muxcy, xorcy)
288 -- inc_muxcy_inst: muxcy
333 -- zero_detector_muxcy: muxcy
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| /dports/lang/pocl/pocl-1.8/examples/accel/rtl/vhdl/ |
| H A D | generic_sru.vhd | 85 -- muxcy xilinx primitive component (carry chain multiplexer) --
86 component muxcy
281 -- simple incrementer, using dedicated hardware (muxcy, xorcy)
285 inc_muxcy_inst: muxcy
328 zero_detector_muxcy: muxcy
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