/dports/net-mgmt/arts++/arts++-1.1.a13/classes/src/ |
H A D | ArtsPortTableData.cc | 223 uint32_t numPorts; in read() local 230 g_ArtsLibInternal_Primitive.ReadUint32(is,numPorts,4); in read() 231 this->_portEntries.reserve(numPorts); in read() 232 for (portNum = 0; portNum < numPorts; portNum++) { in read() 246 uint32_t numPorts; in read() local 268 for (portNum = 0; portNum < numPorts; portNum++) { in read() 288 uint32_t numPorts; in write() local 294 numPorts = this->_portEntries.size(); in write() 295 g_ArtsLibInternal_Primitive.WriteUint32(os,numPorts,4); in write() 312 uint32_t numPorts; in write() local [all …]
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H A D | ArtsSelectedPortTableData.cc | 234 uint32_t numPorts; in read() local 242 g_ArtsLibInternal_Primitive.ReadUint32(is,numPorts,4); in read() 243 this->_portEntries.reserve(numPorts); in read() 244 for (portNum = 0; portNum < numPorts; portNum++) { in read() 258 uint32_t numPorts; in read() local 285 for (portNum = 0; portNum < numPorts; portNum++) { in read() 305 uint32_t numPorts; in write() local 312 numPorts = this->_portEntries.size(); in write() 313 g_ArtsLibInternal_Primitive.WriteUint32(os,numPorts,4); in write() 330 uint32_t numPorts; in write() local [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ |
H A D | chdr_dma_tx.tcl | 2 proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { argument 4 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 16 if { $numPorts < 1 } { 17 puts "ERROR: numPorts invalid: $numPorts" 49 create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq 56 CONFIG.NUM_MI $numPorts \ 62 CONFIG.NUM_SI $numPorts 72 CONFIG.NUM_SI $numPorts \ 77 CONFIG.NUM_PORTS $numPorts \ 126 for {set i 0} {$i < $numPorts} {incr i} {
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H A D | chdr_dma_top.tcl | 7 proc create_hier_cell_dma { parentCell nameHier numPorts } { argument 9 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 21 if { $numPorts < 2 } { 22 puts "ERROR: numPorts invalid: $numPorts" 65 create_hier_cell_rx_dma $hier_obj rx $numPorts 68 create_hier_cell_tx_dma $hier_obj tx $numPorts 73 CONFIG.NUM_REGS $numPorts \ 79 CONFIG.C_SIZE $numPorts \ 85 CONFIG.C_SIZE $numPorts \
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H A D | chdr_dma_rx.tcl | 126 proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { argument 128 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 140 if { $numPorts < 1 } { 141 puts "ERROR: numPorts invalid: $numPorts" 173 create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq 183 CONFIG.NUM_SI $numPorts \ 190 CONFIG.NUM_MI $numPorts \ 197 CONFIG.NUM_MI $numPorts \ 238 CONFIG.NUM_PORTS $numPorts \ 241 create_hier_cell_mtu $hier_obj mtu $numPorts [all …]
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H A D | chdr_dma_frame_size.tcl | 2 proc create_hier_cell_mtu { parentCell nameHier numPorts } { argument 34 create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs 39 for {set i 0} {$i < $numPorts} {incr i} { 45 CONFIG.DIN_WIDTH [expr $numPorts * 32] \
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/n310_ps_bd/ |
H A D | chdr_dma_tx.tcl | 2 proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { argument 4 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 16 if { $numPorts < 1 } { 17 puts "ERROR: numPorts invalid: $numPorts" 49 create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq 56 CONFIG.NUM_MI $numPorts \ 62 CONFIG.NUM_SI $numPorts 72 CONFIG.NUM_SI $numPorts \ 77 CONFIG.NUM_PORTS $numPorts \ 126 for {set i 0} {$i < $numPorts} {incr i} {
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H A D | chdr_dma_top.tcl | 7 proc create_hier_cell_dma { parentCell nameHier numPorts } { argument 9 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 21 if { $numPorts < 2 } { 22 puts "ERROR: numPorts invalid: $numPorts" 65 create_hier_cell_rx_dma $hier_obj rx $numPorts 68 create_hier_cell_tx_dma $hier_obj tx $numPorts 73 CONFIG.NUM_REGS $numPorts \ 79 CONFIG.C_SIZE $numPorts \ 85 CONFIG.C_SIZE $numPorts \
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H A D | chdr_dma_rx.tcl | 126 proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { argument 128 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 140 if { $numPorts < 1 } { 141 puts "ERROR: numPorts invalid: $numPorts" 173 create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq 183 CONFIG.NUM_SI $numPorts \ 190 CONFIG.NUM_MI $numPorts \ 197 CONFIG.NUM_MI $numPorts \ 238 CONFIG.NUM_PORTS $numPorts \ 241 create_hier_cell_mtu $hier_obj mtu $numPorts [all …]
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H A D | chdr_dma_frame_size.tcl | 2 proc create_hier_cell_mtu { parentCell nameHier numPorts } { argument 34 create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs 39 for {set i 0} {$i < $numPorts} {incr i} { 45 CONFIG.DIN_WIDTH [expr $numPorts * 32] \
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ip/e320_ps_bd/ |
H A D | chdr_dma_tx.tcl | 2 proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { argument 4 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 16 if { $numPorts < 1 } { 17 puts "ERROR: numPorts invalid: $numPorts" 49 create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq 56 CONFIG.NUM_MI $numPorts \ 62 CONFIG.NUM_SI $numPorts 72 CONFIG.NUM_SI $numPorts \ 77 CONFIG.NUM_PORTS $numPorts \ 126 for {set i 0} {$i < $numPorts} {incr i} {
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H A D | chdr_dma_top.tcl | 7 proc create_hier_cell_dma { parentCell nameHier numPorts } { argument 9 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 21 if { $numPorts < 2 } { 22 puts "ERROR: numPorts invalid: $numPorts" 65 create_hier_cell_rx_dma $hier_obj rx $numPorts 68 create_hier_cell_tx_dma $hier_obj tx $numPorts 73 CONFIG.NUM_REGS $numPorts \ 79 CONFIG.C_SIZE $numPorts \ 85 CONFIG.C_SIZE $numPorts \
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H A D | chdr_dma_rx.tcl | 126 proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { argument 128 if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { 140 if { $numPorts < 1 } { 141 puts "ERROR: numPorts invalid: $numPorts" 173 create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq 183 CONFIG.NUM_SI $numPorts \ 190 CONFIG.NUM_MI $numPorts \ 197 CONFIG.NUM_MI $numPorts \ 238 CONFIG.NUM_PORTS $numPorts \ 241 create_hier_cell_mtu $hier_obj mtu $numPorts [all …]
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H A D | chdr_dma_frame_size.tcl | 2 proc create_hier_cell_mtu { parentCell nameHier numPorts } { argument 34 create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs 39 for {set i 0} {$i < $numPorts} {incr i} { 45 CONFIG.DIN_WIDTH [expr $numPorts * 32] \
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/dports/lang/intel-compute-runtime/compute-runtime-21.52.22081/level_zero/tools/test/unit_tests/sources/sysman/fabric_port/linux/ |
H A D | test_zes_fabric_port.cpp | 25 static uint32_t numPorts; member in L0::ult::ZesFabricPortFixture 43 .WillByDefault(Return(numPorts)); in SetUp() 56 uint32_t ZesFabricPortFixture::numPorts = 2U; member in L0::ult::ZesFabricPortFixture 63 EXPECT_EQ(count, ZesFabricPortFixture::numPorts); in TEST_F() 73 EXPECT_EQ(count, ZesFabricPortFixture::numPorts); in TEST_F() 78 uint32_t count = ZesFabricPortFixture::numPorts; in TEST_F() 83 EXPECT_EQ(count, ZesFabricPortFixture::numPorts); in TEST_F() 87 uint32_t count = ZesFabricPortFixture::numPorts + 1U; in TEST_F() 92 EXPECT_EQ(count, ZesFabricPortFixture::numPorts); in TEST_F() 96 uint32_t count = ZesFabricPortFixture::numPorts - 1U; in TEST_F() [all …]
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/dports/cad/tkgate/tkgate-2.1/src/tkgate/ |
H A D | igenerate.c | 510 for (j = 0;j < numPorts;j++) { in getSideLabelSizes() 682 for (i = 0;i < numPorts;i++) { in igen_setSymbolPortPositions() 732 for (i = 0;i < numPorts;i++) { in igen_setBlockPortPositions() 767 if (*numPorts > 0) in igen_generate_getInstPorts() 814 *numPorts = numModPorts; in igen_generate_getModPorts() 837 for (i = 0;i < *numPorts;i++) in igen_generate_getModPorts() 881 for (i = 0;i < numPorts;i++) { in igen_generate_positionPorts() 914 int numPorts = 0; in igen_generate_symbol() local 1093 for (i = 0;i < numPorts;i++) { in igen_generate_build() 1167 int numPorts = 0; in igen_generate_initial() local [all …]
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/dports/math/vtk6/VTK-6.2.0/ThirdParty/Twisted/twisted/internet/ |
H A D | protocol.py | 33 numPorts = 0 variable in Factory 69 if not self.numPorts: 73 self.numPorts = self.numPorts + 1 80 if self.numPorts == 0: 84 self.numPorts = self.numPorts - 1 85 if not self.numPorts: 659 numPorts = 0 variable in AbstractDatagramProtocol 672 if not self.numPorts: 676 self.numPorts = self.numPorts + 1 684 self.numPorts = self.numPorts - 1 [all …]
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/dports/devel/py-twisted/Twisted-22.1.0/src/twisted/internet/ |
H A D | protocol.py | 35 numPorts = 0 variable in Factory 70 if not self.numPorts: 74 self.numPorts = self.numPorts + 1 82 if self.numPorts == 0: 86 self.numPorts = self.numPorts - 1 87 if not self.numPorts: 688 numPorts = 0 variable in AbstractDatagramProtocol 702 if not self.numPorts: 706 self.numPorts = self.numPorts + 1 715 self.numPorts = self.numPorts - 1 [all …]
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/dports/net/liveMedia/live/WindowsAudioInputDevice/ |
H A D | WindowsAudioInputDevice_mixer.cpp | 46 unsigned numPorts; member in Mixer 75 portNames->numPorts = WindowsAudioInputDevice::numInputPortsTotal; in getPortNames() 109 for (unsigned j = 0; j < mixer.numPorts; ++j) { in getPortNames() 157 if (mixer.numPorts == 0) continue; in initializeIfNecessary() 159 numInputPortsTotal += mixer.numPorts; in initializeIfNecessary() 162 mixer.numPorts = 0; in initializeIfNecessary() 179 portIndexCount += ourMixers[newMixerId].numPorts; in setInputPort() 234 : hMixer(NULL), dwRecLineID(0), numPorts(0), ports(NULL) { in Mixer() 320 numPorts = mlt.cConnections; 321 for (i = 0; i < numPorts; ++i) { [all …]
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/dports/java/openjdk11/jdk11u-jdk-11.0.13-8-1/test/jdk/sun/management/jmxremote/startstop/ |
H A D | PortAllocator.java | 35 static int[] allocatePorts(final int numPorts) { in allocatePorts() argument 36 int[] ports = new int[numPorts]; in allocatePorts() 37 for (int i = 0; i < numPorts; i++) { in allocatePorts()
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/dports/java/openjdk13/jdk13u-jdk-13.0.10-1-1/test/jdk/sun/management/jmxremote/startstop/ |
H A D | PortAllocator.java | 35 static int[] allocatePorts(final int numPorts) { in allocatePorts() argument 36 int[] ports = new int[numPorts]; in allocatePorts() 37 for (int i = 0; i < numPorts; i++) { in allocatePorts()
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/dports/java/openjdk17/jdk17u-jdk-17.0.1-12-1/test/jdk/sun/management/jmxremote/startstop/ |
H A D | PortAllocator.java | 35 static int[] allocatePorts(final int numPorts) { in allocatePorts() argument 36 int[] ports = new int[numPorts]; in allocatePorts() 37 for (int i = 0; i < numPorts; i++) { in allocatePorts()
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/dports/java/openjdk12/openjdk-jdk12u-jdk-12.0.2-10-4/test/jdk/sun/management/jmxremote/startstop/ |
H A D | PortAllocator.java | 35 static int[] allocatePorts(final int numPorts) { in allocatePorts() argument 36 int[] ports = new int[numPorts]; in allocatePorts() 37 for (int i = 0; i < numPorts; i++) { in allocatePorts()
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/dports/java/openjdk15/jdk15u-jdk-15.0.6-1-1/test/jdk/sun/management/jmxremote/startstop/ |
H A D | PortAllocator.java | 35 static int[] allocatePorts(final int numPorts) { in allocatePorts() argument 36 int[] ports = new int[numPorts]; in allocatePorts() 37 for (int i = 0; i < numPorts; i++) { in allocatePorts()
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/dports/java/openjdk16/jdk16u-jdk-16.0.2-7-1/test/jdk/sun/management/jmxremote/startstop/ |
H A D | PortAllocator.java | 35 static int[] allocatePorts(final int numPorts) { in allocatePorts() argument 36 int[] ports = new int[numPorts]; in allocatePorts() 37 for (int i = 0; i < numPorts; i++) { in allocatePorts()
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