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Searched refs:num_temps (Results 1 – 25 of 346) sorted by relevance

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/dports/science/py-phono3py/phono3py-1.22.3/c/
H A Dpp_collision.c50 const size_t num_temps,
77 const size_t num_temps,
120 num_temps = temperatures->dims[0]; in ppc_get_pp_collision()
162 num_temps, in ppc_get_pp_collision()
196 num_temps, in ppc_get_pp_collision()
246 num_temps = temperatures->dims[0]; in ppc_get_pp_collision_with_sigma()
284 num_temps, in ppc_get_pp_collision_with_sigma()
318 num_temps, in ppc_get_pp_collision_with_sigma()
414 num_temps, in get_collision()
443 for (j = 0; j < num_temps; j++) { in finalize_ise()
[all …]
/dports/www/firefox/firefox-99.0/js/src/jit/
H A DLIROps.yaml86 # num_temps
180 num_temps: 1
185 num_temps: 1
190 num_temps: 2
197 num_temps: 1
221 num_temps: 3
226 num_temps: 2
237 num_temps: 1
249 num_temps: 1
256 num_temps: 1
[all …]
H A DGenerateLIRFiles.py101 name, result_type, operands, arguments, num_temps, call_instruction, mir_op argument
177 if num_temps:
178 for temp in range(num_temps):
196 code += ", {}> {{\\\n".format(num_temps)
263 num_temps = op.get("num_temps", 0)
264 assert num_temps is None or int
281 num_temps,
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/broadcom/compiler/
H A Dvir_register_allocate.c71 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
75 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
153 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
171 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
226 int start_num_temps = c->num_temps; in v3d_spill_reg()
435 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
436 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
437 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
474 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
478 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/lang/clover/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c88 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
92 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
166 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
187 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
266 int start_num_temps = c->num_temps; in v3d_spill_reg()
593 struct node_to_temp_map map[c->num_temps]; in v3d_register_allocate()
594 uint32_t temp_to_node[c->num_temps]; in v3d_register_allocate()
595 uint8_t class_bits[c->num_temps]; in v3d_register_allocate()
633 acc_nodes[i] = c->num_temps + i; in v3d_register_allocate()
637 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
[all …]
/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
380 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
425 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c256 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
257 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
258 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
259 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
269 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
282 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
287 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
306 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
384 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
429 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/broadcom/compiler/
H A Dvir_register_allocate.c140 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
144 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
219 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
232 if (c->num_temps < c->nodes.alloc_count) in ensure_nodes()
271 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
439 c->spill_start_num_temps = c->num_temps; in v3d_spill_reg()
612 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_spill_reg()
621 j < c->num_temps; j++) { in v3d_spill_reg()
953 .alloc_count = c->num_temps, in v3d_register_allocate()
1014 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_register_allocate()
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