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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_gen_for.v28 enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
141 module enflop (clk, oe_e1, a,q);
145 input oe_e1; port
160 always @(posedge clk) oe_r[i] <= oe_e1;